Abstract: A heat-dissipating element having a casing having a closed fluid space. At least a part of the fluid space is filled with a coolant fluid, and the coolant fluid is transformed between a liquid phase and a gas phase by an environment temperature transferred by the casing.

Abstract: A manufacturing method of an electronic package includes the following steps. Multiple chips and a base dielectric layer are provided. A back surface of each chip is fixed to a back surface temporary carrier via a back surface temporary bonding layer. A base dielectric layer surrounds each chip and covers the back surface temporary bonding layer. A material of the base dielectric layer includes a silicate composite material. At least one bridge element is installed on the adjacent chips. An intermediate dielectric layer covering the base dielectric layer, the chips, and the bridge element is formed. Multiple intermediate conductive vias and a redistribution structure are respectively formed on the chips and the intermediate dielectric layer. Multiple conductive bumps are formed on the redistribution structure. The back surface temporary bonding layer and the back surface temporary carrier are removed. An electronic package produced by the manufacturing method is also provided.

Abstract: A manufacturing method of an electronic package includes the following steps. Multiple chips are temporarily fixed to a temporary carrier. At least one bridge element is installed on the adjacent chips. A base dielectric layer covering a temporary bonding layer, the chips, and the bridge element is formed. A material of the base dielectric layer includes a silicate composite material. Multiple base conductive vias and a redistribution structure are respectively formed on the chips and the base dielectric layer. Multiple conductive bumps are formed on the redistribution structure. In addition, an electronic package is also provided, which may be produced by the manufacturing method.

Abstract: A semiconductor device may include a semiconductor substrate and an isolation structure including a first dielectric layer formed over the semiconductor substrate, the first dielectric layer including one or more air gaps, and a first conductive structure formed on the dielectric layer, the conductive structure having a lower surface that faces the semiconductor substrate. Respective air gaps of the one or more air gaps of the first dielectric layer each may be disposed directly between corners of the lower surface of the conductive structure and the semiconductor substrate.

Abstract: A method for forming a semiconductor device structure includes forming a plurality of fin structures from a substrate, each fin structure having first and second semiconductor layers alternatingly stacked, forming an isolation region around the fin structures, forming a first liner layer on exposed surfaces of the fin structures and the isolation region, forming a second liner layer on the first liner layer, selectively removing a portion of the second liner layer so that the second liner layer remains over sidewall of each fin structure, forming an insulating layer on the first and second liner layers, removing the second liner layer, forming a sacrificial gate structure over a portion of the fin structure and the insulating layer, removing a portion of the fin structure not covered by the sacrificial gate structure, forming a source/drain feature such that a gap is formed around and separate the source/drain feature from the insulating layer, and forming a sealing material on the source/drain feature and th

Abstract: A nitride-based wafer CVD device comprises a heat carrier, a nitride-based wafer, and a clamping ring. The heat carrier comprises a carrier surface. The nitride-based wafer is disposed on the carrier surface. The clamping ring is disposed above the carrier surface and the nitride-based wafer. The clamping ring comprises a tilted surface, and a polished surface, and the polished surface is opposite to the tilted surface. The nitride-based wafer has a plurality of HEMT devices. The polished surface and the carrier surface are parallel. A distance between the polished surface and the carrier surface in a first direction is in a range from 1.1 mm to 1.2 mm, and the first direction is parallel to a normal of the carrier surface.

Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

Abstract: A leadless semiconductor package includes an integrated circuit (IC) die having one or more contacts at an active surface facing a mounting surface of the leadless semiconductor package. The leadless semiconductor package further includes a plurality of dual-sided stud structures providing electrical connectivity between the IC die and the mounting surface, each dual-sided stud structure having at least one first conductive pillar structure extending from a corresponding contact at the active surface to a redistribution layer and having at least one second conductive pillar structure extending from a redistribution layer to an edge of the mounting surface, each first conductive pillar structure having a first dimension in a direction parallel to the mounting surface that is less than a corresponding second dimension of each second conductive pillar structure. Solder wettable flanks may be formed at the external sidewall edges of the second conductive pillar structures to facilitate soldering or inspection.

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Abstract: A memory structure includes a pull-down transistor and a pull-up transistor stacked vertically in a Z-direction, a pass-gate transistor and a dummy transistor stacked vertically in the Z-direction, a dielectric structure, a connection structure, and a butt contact. The pull-down transistor and the pull-up transistor share a first gate structure. The pass-gate transistor and the dummy transistor share a second gate structure. The dielectric structure is between the first gate structure and the second gate structure in a Y-direction. The connection structure is over and electrically connected to the first gate structure and is over and electrically isolated from the second gate structure. The connection structure is an L-shape in a Y-Z cross-sectional view. The butt contact is directly over the connection structure and the second gate structure. The butt contact is electrically connected to the connection structure and a source/drain feature of the pass-gate transistor.

Abstract: Embodiments of the present disclosure relate to a SRAM (static random access memory) bit cell. More particularly, embodiments of the present disclosure relate to a single port, 8T SRAM cell with write enhance pass gate transistors. Particularly, two write enhance pass gate transistors are parallelly connected with the pass gate transistors in a standard 6T SRAM cell. The write enhance pass gate transistors are independently controlled from the pass gate transistor using a write enhance word line. In some embodiments, the single port, 8T SRAM cell according to the present disclosure may be implemented by stacked complementary FETs. Empty or dummy PMOS transistors in a standard 6T stacked CFET SRAM cell are used as pass gate transistors or write enhance pass gate transistors.

Abstract: A membrane for a closed system transfer device including a material having 40-50% styrenic block copolymer, 0-10% polypropylene, and 45-60% by weight of mineral oil. The membrane may be utilized in any component of a closed system transfer device or system, such as a syringe adapter, patient connector, vial adapter, IV bag spike, etc. The membrane may also be utilized in scenarios where the cannula of the syringe adapter punctures the membrane and remains in the punctured position for an extended period of time, such as one hour or greater.

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Abstract: A semiconductor device having improved leakage current characteristics includes a semiconductor substrate with first and second nitride-based semiconductor layers so as to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region. A doped III-V nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer. The doped layer has a substantially inverted trapezoidal cross-sectional shape with a longer inverted trapezoid base as an upper surface of the doped III-V nitride-based semiconductor layer and a width of the cross-sectional shape decreasing as the distance away from the upper surface increases. A gate electrode is disposed on or above the doped III-V semiconductor layer and positioned on or above the longer inverted trapezoid base. At least two source/drain (S/D) electrodes are disposed over the second nitride-based semiconductor layer.

Abstract: A pressure sensor includes a substrate, a pressure sensing element, a first signal line, a second signal line, an elastomer, and an opposite substrate. The pressure sensing element includes a first resistor and a second resistor connected in series, a third resistor and a fourth resistor connected in series, a first switch component, and a second switch component. The first and the second resistor are connected in parallel to the third and the fourth resistor. The first switch component is electrically connected between the first and the second resistor. The second switch component is electrically connected between the third and the fourth resistor. The first signal line is electrically connected between the first and the fourth resistor. The second signal line is electrically connected between the second and the third resistor. The elastomer includes a cavity. The first resistor to the fourth resistor overlap with the cavity.

Abstract: An antenna system includes a first antenna element and a second antenna element. The first antenna element includes a first ground element, a first radiation element, a second radiation element, and a third radiation element. The first radiation element has a first feeding point. The second radiation element is coupled to the first ground element. The third radiation element is coupled to the first ground element. The third radiation element is adjacent to the first radiation element and the second radiation element. The second antenna element includes a second ground element, a fourth radiation element, a fifth radiation element, and a sixth radiation element. The fourth radiation element has a second feeding point. The fifth radiation element is adjacent to the fourth radiation element. The fifth radiation element is coupled through the sixth radiation element to the second ground element.

Abstract: A seat belt locking buckle may include a locking buckle and a buckle clip. The locking buckle has a connecting hole at one end to be inserted by the buckle clip; the locking buckle is pivotally connected to a pulling member which is adapted to engage with and secure the buckle clip, and the buckle clip comprises a first penetrated portion at one end, and an elongated tongue portion at the other end to form a horizontal T-shape. Two sides of the tongue are non-parallel to form two sloping edges respectively, and two sloping edges taper gradually from the first penetrated portion toward the end of the tongue to form the tongue in tapered shape, and a hook hole is formed on the narrow end of the tongue to fasten the pulling member thereon.

Abstract: A radiography diagnosis device includes a casing having an opening, a first shielding structure, a dose measuring unit, a transmission-type X-ray source module, and an image receiving assembly. The first shielding structure is disposed in the casing and forms a shielded space located between the transmission-type X-ray source module and the image receiving assembly and corresponding to the opening. An object to be detected is adapted to enter the shielded space through the opening. The transmission-type X-ray source module is disposed in the casing and adapted to provide an X-ray toward the object to be detected in the shielded space. The image receiving assembly is disposed in the casing. During image capturing, the X-ray generated by the transmission-type X-ray source module is received by the dose measuring unit, and the image receiving assembly receives the X-ray passing through the object to be detected at the same time.

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.