Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a transistor region and an one time programmable (OTP) capacitor region, forming a first fin-shaped structure on the transistor region and a second fin-shaped structure on the OTP capacitor region, and then performing an oxidation process to form a gate oxide layer on the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure have different shapes under a cross-section perspective.

Abstract: An electrical connector assembly includes an electrical connector having a card slot and plural terminals extending into the card slot; and a heat dissipation module having a fixing plate at one end thereof, the fixing plate having a notch; wherein the electrical connector has a supporting surface for supporting the fixing plate and a fixing member for mating with the notch, the fixing member includes a spherical or hemispherical head portion for guiding the fixing plate at multiple angles.

Abstract: A method of early detection of Type 1 diabetes uses a quantitative assay to measure biomarkers of autoimmune diseases at specific short regions of a gene sequence. The assay uses amplicon deep sequencing to quantify individual variants of the ERV Group Antigen (Gag) gene associated with an overactive immune response.

Abstract: An anti-twist structure of a voice coil motor includes a base, a lens housing, a first elastic sheet, a second elastic sheet, a magnet, and a yoke member. The lens housing has first margin wall and a second margin wall, and a first protrusion extends from the first margin wall. The yoke member has a first wall, a connection wall, a second wall, and a side wall. The first wall is disposed above the first protrusion, and the second wall is above the first margin wall. The lens housing has a deflectable angle relative to a horizontal reference line. When the lens housing deflects to a maximum value of the deflectable angle, the first margin wall abuts against the second wall and/or the first protrusion abuts against the first wall.

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Abstract: Provided are a sound gathering device for voiceprint monitoring and a preparation method. The sound gathering device is a cone structure and includes a front end portion (1) and a rear end portion (2), the front end portion (1) is trumpet-shaped, an inner wall surface of the front end portion (1) is present a pattern array of a microstructure (3), and the microstructure (3) presenting the pattern array is formed through laser etching. A sound wave frequency monitored by the sound gathering device is 50 Hz˜10 kHz, and a sound wave enters the sound gathering device from an entrance of the front end portion (1), is reflected through the pattern array of the microstructure (3) on the inner wall surface of the front end portion (1), and is transmitted from an exit of the rear end portion (2), and a sound pressure of the exit of the rear end portion (2) is 4 times˜8 times a sound pressure of the entrance of the front end portion (1).

Abstract: A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.

Abstract: An integrated circuit (IC) device includes an interlayer dielectric (ILD), first and second tower structures embedded in the ILD, and first and second ring regions including portions of the ILD that correspondingly extend around the first and second tower structures. Each of the first and second tower structures includes a plurality of conductive patterns in a plurality of metal layers, and a plurality of vias between the plurality of metal layers along a thickness direction of the IC device. The plurality of conductive patterns and the plurality of vias are coupled to each other to form the corresponding first or second tower structure. The first ring region extends around the first tower structure, without extending around the second tower structure.

Abstract: A modulator heater structure may include a plurality of regions having different thicknesses. For example, a heater ring of the modulator heater structure may have a first thickness. A heater pad of the modulator heater structure, that is configured to provide an electrical current to the heater ring, may have a second thickness that is greater than the first thickness. The lesser thickness of the heater ring of the modulator heater structure provides high electrical resistance in the heater ring, which enables the heater ring to quickly and efficiently generate heat. The greater thickness of the heater pad provides low electrical resistance in the second region, which enables the electrical current to be efficiently provided through the heater pad to the heater ring with reduced heat dissipation in the hear pad due to the lower electrical current dissipation in the heater pad.

Abstract: An antenna structure includes a ground element, a feeding radiation element, a first radiation element, a second radiation element, a first coupling branch, and a dielectric substrate. The feeding radiation element has a feeding point. The first radiation element is coupled to the feeding radiation element. The second radiation element is coupled to the feeding radiation element. The second radiation element and the first radiation element substantially extend in opposite directions. The first coupling branch is coupled to a first grounding point on the ground element. The first coupling branch extends across the first radiation element. The first coupling branch includes a first coil portion and a first connection portion.

Abstract: A MEMS structure is provided. The MEMS structure includes a substrate and a backplate, the substrate has an opening portion, and the backplate is disposed on one side of the substrate and has acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate, and the diaphragm extends across the opening portion of the substrate and includes outer ventilation holes and inner ventilation holes arranged in a concentric manner. The outer ventilation holes and the inner ventilation holes are relatively arranged in a ring shape and surround the center of the diaphragm. The MEMS structure further includes a pillar disposed between the backplate and the diaphragm. The pillar prevents the diaphragm from being electrically connected to the backplate.

Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate. The opening portion of the substrate is under the diaphragm, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a pillar structure connected with the backplate and the diaphragm and a protection post structure extending from the backplate into the air gap. From a top view of the backplate, the protection post structure surrounds the pillar structure.

Abstract: A heat-dissipating element having a casing having a closed fluid space. At least a part of the fluid space is filled with a coolant fluid, and the coolant fluid is transformed between a liquid phase and a gas phase by an environment temperature transferred by the casing.

Abstract: A manufacturing method of an electronic package includes the following steps. Multiple chips and a base dielectric layer are provided. A back surface of each chip is fixed to a back surface temporary carrier via a back surface temporary bonding layer. A base dielectric layer surrounds each chip and covers the back surface temporary bonding layer. A material of the base dielectric layer includes a silicate composite material. At least one bridge element is installed on the adjacent chips. An intermediate dielectric layer covering the base dielectric layer, the chips, and the bridge element is formed. Multiple intermediate conductive vias and a redistribution structure are respectively formed on the chips and the intermediate dielectric layer. Multiple conductive bumps are formed on the redistribution structure. The back surface temporary bonding layer and the back surface temporary carrier are removed. An electronic package produced by the manufacturing method is also provided.

Abstract: A manufacturing method of an electronic package includes the following steps. Multiple chips are temporarily fixed to a temporary carrier. At least one bridge element is installed on the adjacent chips. A base dielectric layer covering a temporary bonding layer, the chips, and the bridge element is formed. A material of the base dielectric layer includes a silicate composite material. Multiple base conductive vias and a redistribution structure are respectively formed on the chips and the base dielectric layer. Multiple conductive bumps are formed on the redistribution structure. In addition, an electronic package is also provided, which may be produced by the manufacturing method.

Abstract: A semiconductor device may include a semiconductor substrate and an isolation structure including a first dielectric layer formed over the semiconductor substrate, the first dielectric layer including one or more air gaps, and a first conductive structure formed on the dielectric layer, the conductive structure having a lower surface that faces the semiconductor substrate. Respective air gaps of the one or more air gaps of the first dielectric layer each may be disposed directly between corners of the lower surface of the conductive structure and the semiconductor substrate.

Abstract: A method for forming a semiconductor device structure includes forming a plurality of fin structures from a substrate, each fin structure having first and second semiconductor layers alternatingly stacked, forming an isolation region around the fin structures, forming a first liner layer on exposed surfaces of the fin structures and the isolation region, forming a second liner layer on the first liner layer, selectively removing a portion of the second liner layer so that the second liner layer remains over sidewall of each fin structure, forming an insulating layer on the first and second liner layers, removing the second liner layer, forming a sacrificial gate structure over a portion of the fin structure and the insulating layer, removing a portion of the fin structure not covered by the sacrificial gate structure, forming a source/drain feature such that a gap is formed around and separate the source/drain feature from the insulating layer, and forming a sealing material on the source/drain feature and th

Abstract: A nitride-based wafer CVD device comprises a heat carrier, a nitride-based wafer, and a clamping ring. The heat carrier comprises a carrier surface. The nitride-based wafer is disposed on the carrier surface. The clamping ring is disposed above the carrier surface and the nitride-based wafer. The clamping ring comprises a tilted surface, and a polished surface, and the polished surface is opposite to the tilted surface. The nitride-based wafer has a plurality of HEMT devices. The polished surface and the carrier surface are parallel. A distance between the polished surface and the carrier surface in a first direction is in a range from 1.1 mm to 1.2 mm, and the first direction is parallel to a normal of the carrier surface.

Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

Abstract: A leadless semiconductor package includes an integrated circuit (IC) die having one or more contacts at an active surface facing a mounting surface of the leadless semiconductor package. The leadless semiconductor package further includes a plurality of dual-sided stud structures providing electrical connectivity between the IC die and the mounting surface, each dual-sided stud structure having at least one first conductive pillar structure extending from a corresponding contact at the active surface to a redistribution layer and having at least one second conductive pillar structure extending from a redistribution layer to an edge of the mounting surface, each first conductive pillar structure having a first dimension in a direction parallel to the mounting surface that is less than a corresponding second dimension of each second conductive pillar structure. Solder wettable flanks may be formed at the external sidewall edges of the second conductive pillar structures to facilitate soldering or inspection.