Abstract: A manufacturing method of an electronic package includes the following steps. A first interfacial dielectric layer is formed to cover sides of multiple first conductive vias and multiple second conductive vias. Multiple chips are directly bonded to the first and second conductive vias. A base dielectric layer is formed to fill a gap between the adjacent chips. A bridge element is directly bonded to the first conductive vias, such that the bridge element partially overlaps the adjacent chips respectively. A second interfacial dielectric layer and multiple third conductive vias are formed on the first interfacial dielectric layer and the bridge element. A redistribution circuit structure is formed on the second interfacial dielectric layer and the third conductive vias. Multiple conductive bumps are formed on the redistribution circuit structure. An electronic package is also provided.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first non-conductive layer over a top side a semiconductor die and patterning the first non-conductive layer to form an opening exposing a top surface of a bond of the semiconductor die. A metal trace of a redistribution layer is formed over a portion of the first non-conductive layer and exposed top surface of the bond pad. A surrounding bump metallization (SBM) structure is formed on a portion of the metal trace. The SBM structure includes a plurality of vertical metal wall segments surrounding a central opening.

Abstract: A method for determining the reference internal impedance of a battery includes the following steps: (a) during a sensing period, sensing a battery voltage, a battery current flowing through the battery, and a battery temperature to obtain a sensing result, thereby determining a depth of discharge (DOD); (b) in step (a), comparing the sensing result with a predetermined threshold to determine whether to accept the sensing result; (c) when the sensing result is accepted, calculating a corresponding battery internal impedance based on the sensing result and the depth of discharge; (d) performing regression analysis on the battery internal impedance and a plurality of previous battery internal impedances to obtain a moving average battery internal impedance corresponding to the depth of discharge; and (e) obtaining a corresponding reference battery internal impedance based on the moving average battery internal impedance.

Abstract: A biocompatible magnetic material containing an iron oxide nanoparticle and one or more biocompatible polymers, each having formula (I) below, covalently bonded to the iron oxide nanoparticle: in which each of variables R, L, x, and y is defined herein, the biocompatible magnetic material contains 4-15% Fe(II) ions relative to the total iron ions. Also disclosed in a method of preparing the biocompatible magnetic material.

Abstract: A safety belt structure of racing cars that can be quickly put on and taken off is disclosed. The safety belt structure includes a buckle socket, a buckle clip, and two elastic buckle locks. One end of the buckle socket and the buckle clip are mutually buckled and have a socket part and a clip part. The other ends of the buckle socket and the buckle clip both have a strap-through part and are respectively pivoted with a transverse safety belt. The buckle socket and the buckle clip both have a quick-release buckle clip protruding on one side. One end of the elastic buckle lock has a slot formed to allow the quick-release buckle clip to be inserted into, and the elastic buckle lock can be quickly released by pressing. The other ends of the two elastic buckle locks are formed with a long slot for installing a shoulder safety belt. Accordingly, the two elastic buckle locks can be used to achieve the effect of quickly putting on and taking off the shoulder safety belts.

Abstract: A seat belt locking buckle may include a fastener which is bent to form a first connecting end, and a round first connecting hole penetrating through the first connecting end is connected to a shoulder safety belt. An anti-scratch washer is coupled and connected with the inner periphery of the first connecting hole. The anti-scratch washer is outwardly folded at top and bottom ends to form an upper periphery and a lower periphery, and the anti-scratch washer is secured in the first connecting hole through the upper periphery and the lower periphery, and two round inner fillets are respectively formed at the junctions between the upper periphery and the inner periphery of the anti-scratch washer and between the lower periphery and the inner periphery of the anti-scratch washer.

Abstract: A ultra-high molecular weight siloxane polymer modified membrane for use in closed system transfer device membranes.

Abstract: A self-healing membrane includes a material having a molecular weight greater than 35 k Da, at least 50% by weight of mineral oil, at least 40% styrenic block copolymer, and 0-10% polypropylene. The membrane may be utilized in any component of a closed system transfer device or system, such as a syringe adapter, patient connector, vial adapter, IV bag spike, etc. The membrane may also be utilized in other medical device components and, more specifically, medical device components where the membrane is punctured by a needle.

Abstract: A method of early detection of Type 1 diabetes uses a quantitative assay to measure biomarkers of autoimmune diseases at specific short regions of a gene sequence. The assay uses amplicon deep sequencing to quantify individual variants of the ERV Group Antigen (Gag) gene associated with an overactive immune response.

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Abstract: A heat-dissipating element having a casing having a closed fluid space. At least a part of the fluid space is filled with a coolant fluid, and the coolant fluid is transformed between a liquid phase and a gas phase by an environment temperature transferred by the casing.

Abstract: A manufacturing method of an electronic package includes the following steps. Multiple chips are temporarily fixed to a temporary carrier. At least one bridge element is installed on the adjacent chips. A base dielectric layer covering a temporary bonding layer, the chips, and the bridge element is formed. A material of the base dielectric layer includes a silicate composite material. Multiple base conductive vias and a redistribution structure are respectively formed on the chips and the base dielectric layer. Multiple conductive bumps are formed on the redistribution structure. In addition, an electronic package is also provided, which may be produced by the manufacturing method.

Abstract: A manufacturing method of an electronic package includes the following steps. Multiple chips and a base dielectric layer are provided. A back surface of each chip is fixed to a back surface temporary carrier via a back surface temporary bonding layer. A base dielectric layer surrounds each chip and covers the back surface temporary bonding layer. A material of the base dielectric layer includes a silicate composite material. At least one bridge element is installed on the adjacent chips. An intermediate dielectric layer covering the base dielectric layer, the chips, and the bridge element is formed. Multiple intermediate conductive vias and a redistribution structure are respectively formed on the chips and the intermediate dielectric layer. Multiple conductive bumps are formed on the redistribution structure. The back surface temporary bonding layer and the back surface temporary carrier are removed. An electronic package produced by the manufacturing method is also provided.

Abstract: A semiconductor device may include a semiconductor substrate and an isolation structure including a first dielectric layer formed over the semiconductor substrate, the first dielectric layer including one or more air gaps, and a first conductive structure formed on the dielectric layer, the conductive structure having a lower surface that faces the semiconductor substrate. Respective air gaps of the one or more air gaps of the first dielectric layer each may be disposed directly between corners of the lower surface of the conductive structure and the semiconductor substrate.

Abstract: A method for forming a semiconductor device structure includes forming a plurality of fin structures from a substrate, each fin structure having first and second semiconductor layers alternatingly stacked, forming an isolation region around the fin structures, forming a first liner layer on exposed surfaces of the fin structures and the isolation region, forming a second liner layer on the first liner layer, selectively removing a portion of the second liner layer so that the second liner layer remains over sidewall of each fin structure, forming an insulating layer on the first and second liner layers, removing the second liner layer, forming a sacrificial gate structure over a portion of the fin structure and the insulating layer, removing a portion of the fin structure not covered by the sacrificial gate structure, forming a source/drain feature such that a gap is formed around and separate the source/drain feature from the insulating layer, and forming a sealing material on the source/drain feature and th

Abstract: A nitride-based wafer CVD device comprises a heat carrier, a nitride-based wafer, and a clamping ring. The heat carrier comprises a carrier surface. The nitride-based wafer is disposed on the carrier surface. The clamping ring is disposed above the carrier surface and the nitride-based wafer. The clamping ring comprises a tilted surface, and a polished surface, and the polished surface is opposite to the tilted surface. The nitride-based wafer has a plurality of HEMT devices. The polished surface and the carrier surface are parallel. A distance between the polished surface and the carrier surface in a first direction is in a range from 1.1 mm to 1.2 mm, and the first direction is parallel to a normal of the carrier surface.

Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

Abstract: A leadless semiconductor package includes an integrated circuit (IC) die having one or more contacts at an active surface facing a mounting surface of the leadless semiconductor package. The leadless semiconductor package further includes a plurality of dual-sided stud structures providing electrical connectivity between the IC die and the mounting surface, each dual-sided stud structure having at least one first conductive pillar structure extending from a corresponding contact at the active surface to a redistribution layer and having at least one second conductive pillar structure extending from a redistribution layer to an edge of the mounting surface, each first conductive pillar structure having a first dimension in a direction parallel to the mounting surface that is less than a corresponding second dimension of each second conductive pillar structure. Solder wettable flanks may be formed at the external sidewall edges of the second conductive pillar structures to facilitate soldering or inspection.

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Abstract: A memory structure includes a pull-down transistor and a pull-up transistor stacked vertically in a Z-direction, a pass-gate transistor and a dummy transistor stacked vertically in the Z-direction, a dielectric structure, a connection structure, and a butt contact. The pull-down transistor and the pull-up transistor share a first gate structure. The pass-gate transistor and the dummy transistor share a second gate structure. The dielectric structure is between the first gate structure and the second gate structure in a Y-direction. The connection structure is over and electrically connected to the first gate structure and is over and electrically isolated from the second gate structure. The connection structure is an L-shape in a Y-Z cross-sectional view. The butt contact is directly over the connection structure and the second gate structure. The butt contact is electrically connected to the connection structure and a source/drain feature of the pass-gate transistor.