Patents by Inventor Wen Yuan

Wen Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220148712
    Abstract: A radiation imaging system and a radiation imaging method are provided. The radiation imaging system includes a remote-control module and an imaging device. The imaging device has a radiation isolation cavity. The radiation isolation cavity includes a radiation irradiation area adapted for placing an object under test. The imaging device includes a controller, a radiation source, and a flat panel detector. The radiation source is disposed on a top of the radiation isolation cavity and faces the radiation irradiation area. The flat panel detector is disposed below the radiation exposure area. During a preparation for exposure, the controller turns on the radiation source. When the controller receives an activation signal output by the remote-control module, the controller operates the flat panel detector to obtain a radiation image corresponding to the object under test.
    Type: Application
    Filed: October 14, 2021
    Publication date: May 12, 2022
    Applicant: NanoRay Biotech Co., Ltd.
    Inventor: Wen-Yuan Cheng
  • Publication number: 20220142595
    Abstract: A radiography diagnosis device includes a casing having an opening, a first shielding structure, a dose measuring unit, a transmission-type X-ray source module, and an image receiving assembly. The first shielding structure is disposed in the casing and forms a shielded space located between the transmission-type X-ray source module and the image receiving assembly and corresponding to the opening. An object to be detected is adapted to enter the shielded space through the opening. The transmission-type X-ray source module is disposed in the casing and adapted to provide an X-ray toward the object to be detected in the shielded space. The image receiving assembly is disposed in the casing. During image capturing, the X-ray generated by the transmission-type X-ray source module is received by the dose measuring unit, and the image receiving assembly receives the X-ray passing through the object to be detected at the same time.
    Type: Application
    Filed: October 13, 2021
    Publication date: May 12, 2022
    Applicant: NanoRay Biotech Co., Ltd.
    Inventor: Wen-Yuan Cheng
  • Patent number: 11329382
    Abstract: An antenna structure includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a dielectric substrate. The first radiation element has a positive feeding point. The second radiation element is coupled to the first radiation element. The third radiation element has a negative feeding point. The fourth radiation element is coupled to the third radiation element. The fifth radiation element is floating. The dielectric substrate has a first surface and a second surface which are opposite to each other. The first radiation element and the third radiation element are both disposed on the first surface of the dielectric substrate. The second radiation element, the fourth radiation element, and the fifth radiation element are all disposed on the second surface of the dielectric substrate.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: May 10, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Wen-Yuan Lo, Hui Lin, Jui-Chun Jao, Chen-An Lu
  • Patent number: 11329108
    Abstract: A display device and a manufacturing method thereof are provided. The display device includes a first substrate, a second substrate, first signal lines, second signal lines, a first insulation layer, active components, a display medium, and ultrasonic transducers. The first insulation layer is located between the first signal lines and the second signal lines. Cavities are located in the first insulation layer having thin films located on the cavities. Each of the ultrasonic transducers includes first and second electrodes. A first electrode and a corresponding first signal line belong to a same layer and are electrically connected with each other. A second electrode and a corresponding second signal line belong to a same layer and are electrically connected with each other. A corresponding cavity and a corresponding thin film are sandwiched between the first and second electrodes.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: May 10, 2022
    Assignee: Au Optronics Corporation
    Inventors: Wen-Yuan Li, Tai-Hsiang Huang, Pin-Hsiang Chiu, Zheng-Han Chen
  • Publication number: 20220131268
    Abstract: An antenna structure includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a dielectric substrate. The first radiation element has a positive feeding point. The second radiation element is coupled to the first radiation element. The third radiation element has a negative feeding point. The fourth radiation element is coupled to the third radiation element. The fifth radiation element is floating. The dielectric substrate has a first surface and a second surface which are opposite to each other. The first radiation element and the third radiation element are both disposed on the first surface of the dielectric substrate. The second radiation element, the fourth radiation element, and the fifth radiation element are all disposed on the second surface of the dielectric substrate.
    Type: Application
    Filed: November 16, 2020
    Publication date: April 28, 2022
    Inventors: Wen-Yuan LO, Hui LIN, Jui-Chun JAO, Chen-An LU
  • Publication number: 20220092248
    Abstract: A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.
    Type: Application
    Filed: October 15, 2020
    Publication date: March 24, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Yi-Lin CHUANG, Shi-Wen TAN, Song LIU, Shih-Yao LIN, Wen-Yuan FANG
  • Publication number: 20220080057
    Abstract: A biocompatible magnetic material containing an iron oxide nanoparticle and one or more biocompatible polymers, each having formula (I) below, covalently bonded to the iron oxide nanoparticle: in which each of variables R, L, x, and y is defined herein, the biocompatible magnetic material contains 4-15% Fe(II) ions relative to the total iron ions. Also disclosed in a method of preparing the biocompatible magnetic material.
    Type: Application
    Filed: November 24, 2021
    Publication date: March 17, 2022
    Inventors: Wen-Yuan Hsieh, Yuan-Hung Hsu, Chia-Wen Huang, Ming-Cheng Wei, Chih-Lung Chen, Shian-Jy Wang
  • Patent number: 11267079
    Abstract: Methods and systems for cutting or perforating webs are disclosed. A method of cutting or perforating a web can include providing a web including a film. The film can include a polyolefin polymer and a plurality of particles. The film can include a width and length defining a surface. The method can further include stretching the film to provide a stretched film. Stretching the film can provide a plurality of voids in the stretched film. The method can additionally include providing a laser assembly. The method can include directing abeam of light from the laser assembly upon the surface of the web to cut or perforate the web in at least one location.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 8, 2022
    Assignee: Kimberly-Clark Worldwide, Inc.
    Inventors: Peiguang Zhou, Paul Milbrodt, Wade R. Thompson, Vikram S. Kaul, Wen Yuan
  • Patent number: 11244909
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The first electronic device is disposed on the wiring structure. The second electronic device is disposed on the wiring structure. The first electronic device and the second electronic device are disposed side by side. A gap between the first electronic device and the second electronic device is greater than or equal to about 150 ?m.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: February 8, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Fan-Yu Min, Chen-Hung Lee, Wei-Hang Tai, Yuan-Tzuo Luo, Wen-Yuan Chuang, Chun-Cheng Kuo, Chin-Li Kao
  • Patent number: 11240906
    Abstract: A circuit board heat dissipation system includes circuit board unit that includes a motherboard and a daughterboard, a base seat, and a fastening unit that includes a plurality of first and second fastening components. Each first fastening component extends through the daughterboard and is engaged with the base seat. Each second fastening component includes a long fastener that extends through the base seat and the daughterboard and that is engaged with the motherboard, and a flat washer and a resilient member that are sleeved on the long fastener. The resilient member is disposed between a head portion of the long fastener and the flat washer for biasing the base seat and the daughterboard against the motherboard.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: February 1, 2022
    Assignee: ADVANTECH CO., LTD.
    Inventors: Yu-Chin Liu, Wen-Yuan Yi
  • Patent number: 11227848
    Abstract: A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 18, 2022
    Assignee: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Hsueh-Chung Shelton Lu
  • Patent number: 11208835
    Abstract: An adjusting base for door closer includes a fixing member, an adjusting member, and at least one adjusting unit. The fixing member is configured to be fixed to a surface, and an upper surface of the fixing member is arranged with at least one protrusion. The adjusting member is arranged on the upper surface of the fixing member in an adjustable manner, and configured to be connected to a door closer. The adjusting member is formed with at least one adjusting hole for receiving the at least one protrusion. The at least one adjusting unit is movably arranged on the adjusting member and configured to abut against the at least one protrusion to adjust a relative position between the adjusting member and the fixing member.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: December 28, 2021
    Assignee: Arctek Industrial Co., Ltd.
    Inventor: Wen-Yuan Su
  • Patent number: 11203765
    Abstract: Described are methods and compositions for enhancing drought tolerance in plants. Nucleic acid constructs therefore are also described. Transgenic plants are also provided that exhibit enhanced agronomic properties. The inventors have demonstrated increased drought tolerance in connection with increased expression of the Xa21 gene.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: December 21, 2021
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Wen-Yuan Song, Xiuhua Chen, Xiaoen Huang
  • Publication number: 20210352799
    Abstract: A circuit board heat dissipation system includes circuit board unit that includes a motherboard and a daughterboard, a base seat, and a fastening unit that includes a plurality of first and second fastening components. Each first fastening component extends through the daughterboard and is engaged with the base seat. Each second fastening component includes a long fastener that extends through the base seat and the daughterboard and that is engaged with the motherboard, and a flat washer and a resilient member that are sleeved on the long fastener. The resilient member is disposed between a head portion of the long fastener and the flat washer for biasing the base seat and the daughterboard against the motherboard.
    Type: Application
    Filed: December 3, 2020
    Publication date: November 11, 2021
    Inventors: Yu-Chin LIU, Wen-Yuan YI
  • Publication number: 20210351282
    Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Inventors: Cheng-Yi PENG, Wen-Yuan CHEN, Wen-Hsing HSIEH, Yi-Ju HSU, Jon-Hsu HO, Song-Bor LEE, Bor-Zen TIEN
  • Patent number: 11124832
    Abstract: A serum microRNA (miRNA) marker suitable for early screening and diagnosis of ossification of posterior longitudinal ligament (OPLL) and its application in the diagnostic reagent or kit for the OPLL. Biomarker miRNA-563, miRNA-196b, miRNA-10a and miRNA-129 have high diagnostic value for OPLL, and the development and application of the related serum miRNA biomarker detection reagent kit. It can be applied in the screening of ossification of posterior longitudinal ligament disease, supporting the diagnosis of OPLL more quickly and accurately, evaluate the patient's ossification condition, and may lay down the foundation for improving clinical therapeutic effect.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: September 21, 2021
    Assignee: THE SECOND MILITARY MEDICAL UNIVERSITY
    Inventors: Yang Liu, Chen Xu, Hao Zhang, Wen Yuan, Peng Cao, Huiqiao Wu, Yuanyuan Chen, Xiaolong Shen
  • Publication number: 20210287999
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The first electronic device is disposed on the wiring structure. The second electronic device is disposed on the wiring structure. The first electronic device and the second electronic device are disposed side by side. A gap between the first electronic device and the second electronic device is greater than or equal to about 150 ?m.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 16, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Fan-Yu MIN, Chen-Hung LEE, Wei-Hang TAI, Yuan-Tzuo LUO, Wen-Yuan CHUANG, Chun-Cheng KUO, Chin-Li KAO
  • Patent number: 11101360
    Abstract: A semiconductor device includes a channel region, a source/drain region adjacent to the channel region, and a source/drain epitaxial layer. The source/drain epitaxial layer includes a first epitaxial layer epitaxially formed on the source/drain region, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer. The first epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer and a SiCP layer.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Wen-Hsing Hsieh, Wen-Yuan Chen, Jon-Hsu Ho, Song-Bor Lee, Bor-Zen Tien
  • Patent number: 11081371
    Abstract: A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 3, 2021
    Assignee: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Hsueh-Chung Shelton Lu
  • Patent number: 11069791
    Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Wen-Yuan Chen, Wen-Hsing Hsieh, Yi-Ju Hsu, Jon-Hsu Ho, Song-Bor Lee, Bor-Zen Tien