Abstract: An injection device is disclosed herein. The injection device is utilized to inject a liquid onto a test area of a semiconductor element. The injection device includes a base, a reservoir, a first testing pipe, a cleaning pipe and a liquid-draining pipe. The reservoir set on the base is provided with at least one connecting port and a dropping port, wherein the dropping port is against the test area of the semiconductor element. The first testing pipe, the cleaning pipe and the liquid-draining pipe are connected to at least one connecting port, wherein a first liquid is injected from the first testing pipe into the reservoir, and wherein the a cleaning liquid is injected from the cleaning pipe into the reservoir to clean the reservoir and the test area. The dropping port is utilized to drain off the first testing liquid and the cleaning liquid in the reservoir. A semiconductor testing system utilizing the injection device and its testing method are also provided herein.

Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall, and a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

Abstract: The present publication relates to the wireless signal technologies, and provides methods and systems for wireless signal reinforcement and wireless network load sharing and following. The method for wireless signal reinforcement comprising: a mobile wireless access point moving and measuring the wireless signal strength of other wireless access points received at the location the mobile wireless access point passes through; determining a first location where the wireless signal needs to be reinforced according to the measurement result; and the mobile wireless access point moving to a second location according to the first location, so that the strength of the wireless signal transmitted by the mobile wireless access point from the second location to the first location exceeding the strength of the wireless signal of other wireless access points at the first location.

Abstract: Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.

Abstract: A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.

Abstract: Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.

Abstract: A package substrate has a substrate surface and a chip region on the substrate surface. The package substrate includes circuit layers, conductive vias, and byte region rows. The circuit layers are sequentially spaced below the substrate surface. Each conductive via is connected to at least two of the circuit layers. The byte region rows are arranged side by side sequentially from an edge of the chip region to a center of the chip region, and each byte region row includes byte regions arranged in a row. Each byte region includes pads located on the circuit layer closest to the substrate surface. The pads of the byte regions of the byte region row closer to the edge of the chip region extend from the chip region to an outside of the chip region through traces of the circuit layer closer to the substrate surface.

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Abstract: An injection device is disclosed herein. The injection device is utilized to inject a liquid onto a test area of a semiconductor element. The injection device includes a base, a reservoir, a first testing pipe, a cleaning pipe and a liquid-draining pipe. The reservoir set on the base is provided with at least one connecting port and a dropping port, wherein the dropping port is against the test area of the semiconductor element. The first testing pipe, the cleaning pipe and the liquid-draining pipe are connected to at least one connecting port, wherein a first liquid is injected from the first testing pipe into the reservoir, and wherein the a cleaning liquid is injected from the cleaning pipe into the reservoir to clean the reservoir and the test area. The dropping port is utilized to drain off the first testing liquid and the cleaning liquid in the reservoir. A semiconductor testing system utilizing the injection device and its testing method are also provided herein.

Abstract: The present invention provides an automated system for exchanging polish plate, comprising a loading chamber to store polish plates ready for use, and the automated system has a mechanical arm to pick up and place polish plates between a test chamber and the loading chamber. The present invention realizes automated exchange of polish plates.

Abstract: A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.

Abstract: The present invention provides a probing system, which utilizes a suction nozzle to suck a wafer in probing. A relative distance between the suction nozzle and the probes can be adjusted according the conditions of the probing system, so the system extends the usage life.

Abstract: Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.

Abstract: A radiography diagnosis device includes a casing having an opening, a first shielding structure, a dose measuring unit, a transmission-type X-ray source module, and an image receiving assembly. The first shielding structure is disposed in the casing and forms a shielded space located between the transmission-type X-ray source module and the image receiving assembly and corresponding to the opening. An object to be detected is adapted to enter the shielded space through the opening. The transmission-type X-ray source module is disposed in the casing and adapted to provide an X-ray toward the object to be detected in the shielded space. The image receiving assembly is disposed in the casing. During image capturing, the X-ray generated by the transmission-type X-ray source module is received by the dose measuring unit, and the image receiving assembly receives the X-ray passing through the object to be detected at the same time.

Abstract: A radiation imaging system and a radiation imaging method are provided. The radiation imaging system includes a remote-control module and an imaging device. The imaging device has a radiation isolation cavity. The radiation isolation cavity includes a radiation irradiation area adapted for placing an object under test. The imaging device includes a controller, a radiation source, and a flat panel detector. The radiation source is disposed on a top of the radiation isolation cavity and faces the radiation irradiation area. The flat panel detector is disposed below the radiation exposure area. During a preparation for exposure, the controller turns on the radiation source. When the controller receives an activation signal output by the remote-control module, the controller operates the flat panel detector to obtain a radiation image corresponding to the object under test.

Abstract: An antenna structure includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a dielectric substrate. The first radiation element has a positive feeding point. The second radiation element is coupled to the first radiation element. The third radiation element has a negative feeding point. The fourth radiation element is coupled to the third radiation element. The fifth radiation element is floating. The dielectric substrate has a first surface and a second surface which are opposite to each other. The first radiation element and the third radiation element are both disposed on the first surface of the dielectric substrate. The second radiation element, the fourth radiation element, and the fifth radiation element are all disposed on the second surface of the dielectric substrate.

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a first substrate, a second substrate, first signal lines, second signal lines, a first insulation layer, active components, a display medium, and ultrasonic transducers. The first insulation layer is located between the first signal lines and the second signal lines. Cavities are located in the first insulation layer having thin films located on the cavities. Each of the ultrasonic transducers includes first and second electrodes. A first electrode and a corresponding first signal line belong to a same layer and are electrically connected with each other. A second electrode and a corresponding second signal line belong to a same layer and are electrically connected with each other. A corresponding cavity and a corresponding thin film are sandwiched between the first and second electrodes.

Abstract: An antenna structure includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a dielectric substrate. The first radiation element has a positive feeding point. The second radiation element is coupled to the first radiation element. The third radiation element has a negative feeding point. The fourth radiation element is coupled to the third radiation element. The fifth radiation element is floating. The dielectric substrate has a first surface and a second surface which are opposite to each other. The first radiation element and the third radiation element are both disposed on the first surface of the dielectric substrate. The second radiation element, the fourth radiation element, and the fifth radiation element are all disposed on the second surface of the dielectric substrate.