Abstract: A vertical oxide-semiconductor transistor is proposed by the present invention, including an insulating substrate, a source in the insulating substrate, a gate on the insulating substrate, wherein the gate surrounds the source and forms a recess on the source, an inner spacer on an inner sidewall of the gate in the recess, an oxide-semiconductor layer on the inner spacer and the source and directly contacts the source, a filling oxide on the oxide-semiconductor layer and filling in the recess, and a drain on the oxide-semiconductor layer and filling oxide and directly connecting with the oxide-semiconductor layer, wherein the drain completely covers the source and partially overlaps the gate.

Abstract: A method and system of evaluating a valid analysis region of a specific scene, wherein the method and system performs image analyses on continuous images/frames of a specific scene to obtain detectable object or event information therein, so as to generate a closed valid analysis region to reduce the overall data and loading of image analyses during actual monitoring, processing and analyzing of the specific scene.

Abstract: A method of improving endurance of a NOR flash is provided. The NOR flash includes a substrate, a well formed in the substrate, a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate sequentially stacked on the substrate, and a source and a drain formed in the well. The method includes the following steps. An erase time of the NOR flash is detected. In the case where the erase time exceeds a predetermined value, the source is brought into a floating state, a negative voltage is applied to the control gate, and a positive voltage is applied to the well to perform Joule heating on a drain side.

Abstract: A dynamic random access memory (DRAM) device includes a substrate, multiple write word lines, multiple read word lines, multiple write bit lines, multiple read bit lines, and multiple memory device layers and a method forms the same. The write word lines and the read word lines extend toward a first direction. The write bit lines and the read bit lines extend toward a second direction, and the second direction is orthogonal to the first direction. The memory device layers are disposed on the substrate and are stacked along a normal direction of the substrate, and each of the memory device layers includes multiple memory cells. The memory cells include write transistors and read transistors, wherein a source of the corresponding write transistor is electrically connected to a gate of the corresponding read transistor to form a storage node.

Abstract: A dynamic random access memory device and a method for forming the same are provided. The dynamic random access memory device includes a substrate, multiple word lines, multiple bit lines, and multiple memory device layers. The word lines extend toward a first direction. The bit lines extend toward a second direction. The second direction is orthogonal to the first direction. The memory device layers are disposed on the substrate and stacked in a normal direction of the substrate. Each memory device layers includes multiple memory cells and a capacitor voltage transmission line. The memory cells include a thin film transistor and a capacitor. Each memory cells is electrically connected to a corresponding word line and a corresponding bit line. The capacitor voltage transmission line is electrically connected to the capacitor. The word lines or the bit lines extend in a same direction as the capacitor voltage transmission line.

Abstract: A vertical oxide-semiconductor transistor is proposed by the present invention, including an insulating substrate, a source in the insulating substrate, a gate on the insulating substrate, wherein the gate surrounds the source and forms a recess on the source, an inner spacer on an inner sidewall of the gate in the recess, an oxide-semiconductor layer on the inner spacer and the source and directly contacts the source, a filling oxide on the oxide-semiconductor layer and filling in the recess, and a drain on the oxide-semiconductor layer and filling oxide and directly connecting with the oxide-semiconductor layer, wherein the drain completely covers the source and partially overlaps the gate.

Abstract: A method of improving endurance of a NOR flash is provided. The NOR flash includes a substrate, a well formed in the substrate, a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate sequentially stacked on the substrate, and a source and a drain formed in the well. The method includes the following steps. An erase time of the NOR flash is detected. In the case where the erase time exceeds a predetermined value, the source is brought into a floating state, a negative voltage is applied to the control gate, and a positive voltage is applied to the well to perform Joule heating on a drain side.

Abstract: During a testing of a circuit design, an adaptive clock model and a voltage noise model are utilized within the computer implemented method of the testing environment in order to determine the dynamic effects of voltage variation and adaptive clock on the timing of the circuit design. The computer implemented method uses a hybrid stage that incorporates both a graph-based approach and a path-based approach may also be incorporated into the testing environment in order to maximize a performance of the testing of the circuit design.

Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.

Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.

Abstract: In the memory structure, a pair of gate stack structures is on a first dielectric layer and separated from each other. Each of the gate stack structures includes a word line and a second dielectric layer. A third dielectric layer is on the sidewall of the gate stack structures. A pair of floating gates is between the gate stack structures. Each of the floating gates is on the third dielectric layer on the sidewall of the corresponding gate stack structure. The top surface of the floating gates is not higher than the that of the second dielectric layer. A fourth dielectric layer covers the first and third dielectric layers, and the floating gates. A control gate is on the fourth dielectric layer between the floating gates. A doped region is in the substrate beside the gate stack structures. An erase gate is above the control gate and the floating gates.

Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.

Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.

Abstract: A method and system of evaluating a valid analysis region of a specific scene, wherein the method and system performs image analyses on continuous images/frames of a specific scene to obtain detectable object or event information therein, so as to generate a closed valid analysis region to reduce the overall data and loading of image analyses during actual monitoring, processing and analyzing of the specific scene.

Abstract: Introduced herein is an improved technique of recovering system frequency margin via distributed CPMs. The introduced technique creates and distributes multiple sets of always sensitized critical path replicas across a chip and monitors them for timing failure. The introduced technique takes feedback from these critical path replicas and dynamically boosts the clock frequency of the chip to remove the margin. The introduced technique provides more accurate and more comprehensive coverage of a chip performance.

Abstract: In the memory structure, a pair of gate stack structures is on a first dielectric layer and separated from each other. Each of the gate stack structures includes a word line and a second dielectric layer. A third dielectric layer is on the sidewall of the gate stack structures. A pair of floating gates is between the gate stack structures. Each of the floating gates is on the third dielectric layer on the sidewall of the corresponding gate stack structure. The top surface of the floating gates is not higher than the that of the second dielectric layer. A fourth dielectric layer covers the first and third dielectric layers, and the floating gates. A control gate is on the fourth dielectric layer between the floating gates. A doped region is in the substrate beside the gate stack structures. An erase gate is above the control gate and the floating gates.

Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.

Abstract: A power controller in collocation with a rectification unit, a transformer, a switching unit, a current sensing resistor, an output rectification unit, and an output capacitor is disclosed, and includes a working voltage pin, a ground pin, a PWM driving pin, a current sensing pin, and a load feedback pin for converting an external AC input power into an output power to supply a load. In particular, the power controller simultaneously performs active detection on load power to provide overload protection. Specifically, a load feedback signal related to a load power and a threshold load voltage representative of a preset threshold load power is compared, and a power counter representative of a calculated load power is increased by one, decreased by one, or kept without change according to the comparison result. Then, the power counter is employed to determine whether an overload abnormal event occurs.

Abstract: Various embodiments of the disclosure disclosed herein provide techniques for pre-silicon testing of a design for an integrated circuit. A pre-silicon testing system identifies one or more critical paths included in the integrated circuit. The pre-silicon testing system performs a based noise simulation to generate one or more voltage waveforms at each gate associated with the one or more critical paths. The pre-silicon testing system applies the one or more voltage waveforms to one or more netlists corresponding to the one or more critical paths to generate one or more modified netlists. The pre-silicon testing system performs a timing analysis on the one or more modified netlists to determine a set of slack times that correspond to a set of voltages applied to the integrated circuit. The pre-silicon testing system determines a first critical path that has a lowest slack time relative to all other critical paths.

Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.