Abstract: Various embodiments of the disclosure disclosed herein provide techniques for pre-silicon testing of a design for an integrated circuit. A pre-silicon testing system identifies one or more critical paths included in the integrated circuit. The pre-silicon testing system performs a based noise simulation to generate one or more voltage waveforms at each gate associated with the one or more critical paths. The pre-silicon testing system applies the one or more voltage waveforms to one or more netlists corresponding to the one or more critical paths to generate one or more modified netlists. The pre-silicon testing system performs a timing analysis on the one or more modified netlists to determine a set of slack times that correspond to a set of voltages applied to the integrated circuit. The pre-silicon testing system determines a first critical path that has a lowest slack time relative to all other critical paths.

Abstract: A memory structure and a manufacturing method thereof are provided. In the memory structure, a first dielectric layer is disposed on a substrate; a pair of gate stack structures is disposed on the first dielectric layer and each gate stack structure includes a word line, an erase gate and a second dielectric layer; a third dielectric layer is disposed on the surfaces of the gate stack structures; a pair of floating gates is disposed between the gate stack structures and located respectively on sidewalls of the gate stack structures, and top surfaces of the floating gates are lower than those of the erase gates; a fourth dielectric layer covers the first and third dielectric layers and the floating gates; a control gate is disposed on the fourth dielectric layer between the floating gates; and a doped region is disposed in the substrate beside the gate stack structures.

Abstract: A memory device and a manufacturing method are provided. The memory device includes a substrate, first and second word lines, first and second charge trapping layers, a first drain region and a first source region. The substrate has first and second recesses extending along a first direction. The first and second word lines are respectively disposed in the first and second recesses. The first and second charge trapping layers are respectively disposed in the first and second recesses. The first charge trapping layer is located between the first word line and a sidewall of the first recess. The second charge trapping layer is located between the second word line and a sidewall of the second recess. The first and second drain regions are disposed in the substrate, and respectively extending between the first and the second charge trapping layers along a second direction.

Abstract: A memory structure and a manufacturing method thereof are provided. In the memory structure, a first dielectric layer is disposed on a substrate; a pair of gate stack structures is disposed on the first dielectric layer and each gate stack structure includes a word line, an erase gate and a second dielectric layer; a third dielectric layer is disposed on the surfaces of the gate stack structures; a pair of floating gates is disposed between the gate stack structures and located respectively on sidewalls of the gate stack structures, and top surfaces of the floating gates are lower than those of the erase gates; a fourth dielectric layer covers the first and third dielectric layers and the floating gates; a control gate is disposed on the fourth dielectric layer between the floating gates; and a doped region is disposed in the substrate beside the gate stack structures.

Abstract: A memory device and a manufacturing method are provided. The memory device includes a substrate, first and second word lines, first and second charge trapping layers, a first drain region and a first source region. The substrate has first and second recesses extending along a first direction. The first and second word lines are respectively disposed in the first and second recesses. The first and second charge trapping layers are respectively disposed in the first and second recesses. The first charge trapping layer is located between the first word line and a sidewall of the first recess. The second charge trapping layer is located between the second word line and a sidewall of the second recess. The first and second drain regions are disposed in the substrate, and respectively extending between the first and the second charge trapping layers along a second direction.

Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.

Abstract: Disclosed is a method of acquiring input and output voltage information by employing a pulse width modulation (PWM) controller, which is in collocation with an input power processing unit, a primary inductor, a switch element, a current-sensing resistor, an output rectifier, and an output filter for converting an alternating current input power into an rectified input power and an output power, and the output power supplies an external load. A current-sensing signal is specifically disposed and applied to calculation of the input voltage and output voltage of the rectified input power when the switch element is turned on and off, respectively. Thus, no resistive voltage divider is needed, and power consumption at no load is greatly improved.

Abstract: Disclosed is an integrated PFC and PWM controller with a plurality of frequency-load curves to minimize the no-load power consumption and maximize 4-point average efficiencies. The controller selects a frequency-load curve among the plurality of frequency-load and controls the PFC stage and the PWM stage to operate in HM, BM, DCM, or CCM based on the combined result from the input voltage and the output load sense signal, fetched respectively from the input terminal of the PFC stage and the output terminal of the PWM stage. The controller has the PSU operate in HM in case of no load, and operate in BM, DCM or CCM as the load increases across the flyback out rail.

Abstract: Disclosed is a PWM controller with programmable switching frequency for PSR/SSR flyback converter so as to maximize the performance-to-cost ratio by tailor-making the switching frequency as a non-decreasing function of the output load and the maximum switching frequency as a non-increasing function of the input voltage, leading to a plurality of programmable voltage-dependent frequency-load curves, making possible the downsizing of flyback transformer while facilitating the simultaneous compliance with DoE and CoC efficiency requirements.

Abstract: A resistive random access memory device and a method for fabricating the same are presented. The resistive random access memory device includes a first electrode having a first dopant within. A second electrode is disposed on the first electrode. A resistive switching layer is disposed between the first electrode and the second electrode.

Abstract: Disclosed is a PWM controller with programmable switching frequency for PSR/SSR flyback converter so as to maximize the performance-to-cost ratio by tailor-making the switching frequency as a non-decreasing function of the output load and the maximum switching frequency as a non-increasing function of the input voltage, leading to a plurality of programmable voltage-dependent frequency-load curves, making possible the downsizing of flyback transformer while facilitating the simultaneous compliance with DoE and CoC efficiency requirements.

Abstract: Disclosed is an isolated power conversion system for providing a function of isolated power conversion by converting an AC power into a DC output power, and a rectifying unit, a transformer, a switching transistor, a first pulse width modulation (PWM) controller, a second PWM controller, an output unit and a signal blocking unit are included. The signal blocking unit is employed as a connection interface between the first and second PWM controllers to provide digital signal for communication. Noise margin and stability of electrical operation are improved to avoid malfunction. Overall, the present invention greatly enhances stability of power conversion and secures quality of electrical signal.

Abstract: Disclosed is a dual-mode operation controller in collocation with an input capacitor, a flyback transformer, a first primary-side switch, a second primary-side switch, a current-sensing resistor, a primary-side voltage-sensing unit, a secondary-side rectifier, and an output capacitor as a Primary-Side Regulation (PSR) flyback converter, which is dynamically controlled to operate in two operating modes, including Quasi-Resonant-Discontinuous Conduction Mode (QR-DCM) and Continuous Conduction Mode (CCM), in accordance with a loading condition so as to convert a unregulated DC input voltage source into a regulated DC output voltage source. The dual-mode operation controller has at least 5 pins, and the flyback transformer includes a primary-side winding, a secondary-side winding, and an auxiliary winding.

Abstract: Disclosed is an integrated PFC and PWM controller with a plurality of frequency-load curves to minimize the no-load power consumption and maximize 4-point average efficiencies. The controller dynamically ushers the PFC and the PWM stage into HM, BM, DCM, or CCM on the most appropriate one among the plural frequency-load curves, cherry-picked based on the combined result from the input voltage and the output load sense signals, fetched from the input and the output terminals of the PFC and the PWM stage. All in all, the controller has the PSU operate in HM in case of no load, in BM in case of little load, in DCM in case of light load, or in CCM in case of heavy load across the flyback output rail.

Abstract: A resistive random access memory device and a method for fabricating the same are presented. The resistive random access memory device includes a first electrode having a first dopant within. A second electrode is disposed on the first electrode. A resistive switching layer is disposed between the first electrode and the second electrode.

Abstract: A resistive random access memory device and a method for fabricating the same are presented. The resistive random access memory device includes a first electrode having a first dopant within. A second electrode is disposed on the first electrode. A resistive switching layer is disposed between the first electrode and the second electrode.

Abstract: Disclosed is an isolated power conversion system for providing a function of isolated power conversion by converting an AC power into a DC output power, and a rectifying unit, a transformer, a switching transistor, a first pulse width modulation (PWM) controller, a second PWM controller, an output unit and a signal blocking unit are included. The signal blocking unit is employed as a connection interface between the first and second PWM controllers to provide digital signal for communication. Noise margin and stability of electrical operation are improved to avoid malfunction. Overall, the present invention greatly enhances stability of power conversion and secures quality of electrical signal.

Abstract: A power factor correction control device for dynamically sensing and boost regulation includes a rectifying unit, a transformer, a digital regulation controller, a driving element, a sensing resistor, an output diode and an output capacitor. The control device converts an AC input power into a DC output power so as to supply an external load. The transformer includes a primary coil and an auxiliary coil, the controller employs an auxiliary voltage from the auxiliary coil to calculate the current input voltage and the current output voltage to implement feedback control for the driving element. The driving element is thus turned on and off by the controller to achieve boost function such that the output voltage is greater than the input voltage. The present invention obtains the input voltage and the output voltage by calculation without any sensing resistor, thereby reducing power consumption and increasing power conversion efficiency.

Abstract: A power converting apparatus with dynamical driving adjustment includes a rectifying unit, a power factor correction unit, a power conversion unit and a feedback unit. The rectifying unit rectifies an AC input power to generate and transfer a DC power to the power factor correction unit for performing power factor correction. A power factor correction power is generated and transferred to the power conversion unit. The feedback unit is electrically connected to the power conversion unit to form a closed control loop. A PWM driving controller of the power conversion unit performs an adjustment process to control a switching transistor based on a feedback signal from the feedback unit, and the power conversion unit converts the power factor correction power into an output power supplied to an external load. Thus, the margin for electromagnetic interference is increased, and both switching loss and conduction loss are considerably reduced.

Abstract: A power control apparatus with dynamical adjustment of driving capability for converting an input power into an output power includes a transformer, a switch transistor connected to the transformer, a pulsed width modulation (PWM) driving controller generating a PWM signal and connected to the switch transistor, an isolation element, an output diode and an output capacitor. The first side coil of the transformer and the switch transistor are connected to the input power, the second side coil of the transformer is connected to the output diode and further connected to the output capacitor and an external load. The isolation element converts the output power into a feedback signal providing the PWM driving controller to dynamically control the PWM driving signal through adjustment so as to implement the optimal turn-on current for the switch transistor. Therefore, electrical performance and conversion efficiency are greatly improved by reducing the switching loss.