Abstract: A power control apparatus with dynamical adjustment of driving capability for converting an input power into an output power includes a transformer, a switch transistor connected to the transformer, a pulsed width modulation (PWM) driving controller generating a PWM signal and connected to the switch transistor, an isolation element, an output diode and an output capacitor. The first side coil of the transformer and the switch transistor are connected to the input power, the second side coil of the transformer is connected to the output diode and further connected to the output capacitor and an external load. The isolation element converts the output power into a feedback signal providing the PWM driving controller to dynamically control the PWM driving signal through adjustment so as to implement the optimal turn-on current for the switch transistor. Therefore, electrical performance and conversion efficiency are greatly improved by reducing the switching loss.

Abstract: A resistive random access memory device and a method for fabricating the same are presented. The resistive random access memory device includes a first electrode having a first dopant within. A second electrode is disposed on the first electrode. A resistive switching layer is disposed between the first electrode and the second electrode.

Abstract: An electronic device is provided, which includes a light sensor, an algorithm engine, an adjustment engine, and a display. The light sensor detects an ambient brightness around the electronic device. The algorithm engine is coupled to the light sensor. The algorithm engine determines at least one adjustment function according to the ambient brightness. The adjustment engine is coupled to the algorithm engine. The adjustment engine adjusts the luminance component of each pixel of an image according to the at least one adjustment function to enhance the brightness and/or the contrast of the image. The display is coupled to the adjustment engine for displaying the adjusted image.

Abstract: Provided is a resistance memory device including a dielectric layer, a conductive layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on a substrate and has a first opening constituted by a lower opening and an upper opening. The conductive layer fills up the lower opening. The bottom electrode is disposed on the bottom and on at least a portion of the sidewall of the upper opening. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the top electrode and the bottom electrode.

Abstract: A sine pulse width modulation controller includes an edge detection unit for receiving a feedback input signal from the external electrical device to generate an edge signal, a register unit for storing and outputting a parameter signal, an angle increasing unit for receiving the edge signal and the parameter signal, determining cycles of pulse width modulation and generating an angle signal, a sine calculation unit for receiving the angle signal and performing a recursive algorithm based on the angle signal to implement the recursive algorithm so as to generate a sine calculation value, a multiplication unit for receiving the sine calculation value which is then further multiplied by the amplitude signal from the register unit to generate a pulse width signal, and a sine output unit receiving the pulse width signal to generate driving signals for driving the external electrical device to generate a sine terminal voltage.

Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.

Abstract: Provided is a resistance memory device including a dielectric layer, a conductive layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on a substrate and has a first opening constituted by a lower opening and an upper opening. The conductive layer fills up the lower opening. The bottom electrode is disposed on the bottom and on at least a portion of the sidewall of the upper opening. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the top electrode and the bottom electrode.

Abstract: Provided is a resistance memory device including a dielectric layer, a conductive layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on a substrate and has a first opening constituted by a lower opening and an upper opening. The conductive layer fills up the lower opening. The bottom electrode is disposed on the bottom and on at least a portion of the sidewall of the upper opening. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the top electrode and the bottom electrode.

Abstract: A method for fabricating a semiconductor device is described. A plurality of isolation structures is formed in a substrate. The isolation structures are arranged in parallel and extend along a first direction. A well of a first conductive type is formed in the substrate. A plurality of first doped regions of a second conductive type is formed in the well. Each of the first doped regions is formed between two adjacent isolation structures. A plurality of gates of the second conductive type is formed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is connected to one of the gates. A plurality of second doped regions of the first conductive type is formed in the well. Each of the second doped regions is formed in the first doped regions between two adjacent gates.

Abstract: A synchronous rectifying buck-boost converter includes a controller, first and second transistors, an inductor and a capacitor. The controller is connected to the gates of the first and second transistors for controlling ON/OFF of the first and second transistors, and further controls the current of the inductor and charge/discharge of the capacitor. The first and second transistors connected in series are connected to the controller and the inductor. The inductor is connected to a first external power unit or a first external loading device. The drain of the first transistor is connected to a second external power unit or a second external loading device such that a low-voltage input power of the first external power unit is converted to a high-voltage output power or a high-voltage input power of the second external power unit is converted to a low-voltage output power.

Abstract: A digital pulse width modulation controller includes a pulse width modulation controller, a selection unit having at least one selector, a comparison unit having at least one comparator, and a signal conversion unit having at least one digital-to-analog converter. The digital-to-analog converter generates a reference current and/or voltage. The comparator receives the reference current and/or voltage, and performs a comparison operation to generate a comparison signal based on a feedback signal. The selector selects one selection signal to input into the pulse width modulation controller, which receives other parameters set by a user or the system at the same time so as to control characteristics of the digital pulse width modulation signals, thereby improving the electric properties of a loading circuit.

Abstract: An electronic apparatus and a backlight brightness control method thereof are provided. The control method includes the following steps. Detection of an ambient brightness for the electronic apparatus is made to output an ambient brightness signal. Next, whether to adjust the backlight brightness for the display is determined according to a comparison between the ambient brightness signal and a current backlight brightness. If the comparison result indicates that the ambient brightness decrement is lower than a decrement threshold, then an adjustment value is selected from a plurality of step sizes according to the current backlight brightness to decrease the backlight brightness gradually, so that the backlight brightness changes towards a target backlight brightness corresponding to the ambient brightness signal. The step sizes include a first step size and a second step size. The backlight brightness for the display is adjusted according to the current backlight brightness and the adjustment value.

Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.

Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.

Abstract: Provided is a resistance memory device including a dielectric layer, a conductive layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on a substrate and has a first opening constituted by a lower opening and an upper opening. The conductive layer fills up the lower opening. The bottom electrode is disposed on the bottom and on at least a portion of the sidewall of the upper opening. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the top electrode and the bottom electrode.

Abstract: The invention provides a camera system. In one embodiment, the camera system comprises a camera module and a processor. The camera module photographs a target object according to a focal length to generate an image. The processor comprises an extending-lens-depth-of-filed (EDOF) module and an auto focus module. The EDOF module processes the image according to an EDOF process to generate an EDOF image. The auto focus module adjusts the focal length of the camera module according to an auto focus process.

Abstract: A digital pulse width modulation controller includes a pulse width modulation controller, a selection unit having at least one selector, a comparison unit having at least one comparator, and a signal conversion unit having at least one digital-to-analog converter. The digital-to-analog converter generates a reference current and/or voltage. The comparator receives the reference current and/or voltage, and performs a comparison operation to generate a comparison signal based on a feedback signal. The selector selects one selection signal to input into the pulse width modulation controller, which receives other parameters set by a user or the system at the same time so as to control characteristics of the digital pulse width modulation signals, thereby improving the electric properties of a loading circuit.

Abstract: An electronic device is provided, which includes a light sensor, an algorithm engine, an adjustment engine, and a display. The light sensor detects an ambient brightness around the electronic device. The algorithm engine is coupled to the light sensor. The algorithm engine determines at least one adjustment function according to the ambient brightness. The adjustment engine is coupled to the algorithm engine. The adjustment engine adjusts the luminance component of each pixel of an image according to the at least one adjustment function to enhance the brightness and/or the contrast of the image. The display is coupled to the adjustment engine for displaying the adjusted image.

Abstract: A sine pulse width modulation controller includes an edge detection unit for receiving a feedback input signal from the external electrical device to generate an edge signal, a register unit for storing and outputting a parameter signal, an angle increasing unit for receiving the edge signal and the parameter signal, determining cycles of pulse width modulation and generating an angle signal, a sine calculation unit for receiving the angle signal and performing a recursive algorithm based on the angle signal to implement the recursive algorithm so as to generate a sine calculation value, a multiplication unit for receiving the sine calculation value which is then further multiplied by the amplitude signal from the register unit to generate a pulse width signal, and a sine output unit receiving the pulse width signal to generate driving signals for driving the external electrical device to generate a sine terminal voltage.

Abstract: A synchronous rectifying buck-boost converter includes a controller, first and second transistors, an inductor and a capacitor. The controller is connected to the gates of the first and second transistors for controlling ON/OFF of the first and second transistors, and further controls the current of the inductor and charge/discharge of the capacitor. The first and second transistors connected in series are connected to the controller and the inductor. The inductor is connected to a first external power unit or a first external loading device. The drain of the first transistor is connected to a second external power unit or a second external loading device such that a low-voltage input power of the first external power unit is converted to a high-voltage output power or a high-voltage input power of the second external power unit is converted to a low-voltage output power.