Abstract: A process for manufacturing a MOSFET having a shallow junction of a doped region includes preparing an intermediate wafer product, applying an oxide layer on said intermediate wafer product, introducing into a dopant around an interface between said oxide layer and said intermediate wafer product, and driving said dopant into said intermediate wafer product to form a MOSFET having a relatively shallow junction of a doped region. This invention offers a simplified, efficient, and cost-effective process to obtain a MOSFET having a relatively shallow junction of a doped region and being free from electrical leakage possibly occurred at the junction.

Abstract: A self aligned lateral BJT is disclosed which has a lightly doped first region of a first conductivity type, e.g., P-type. A heavily doped polysilicon region, of a second conductivity type, e.g., N-type, is provided on a portion of a surface of the first region. A heavily doped second region of the second conductivity type, is disposed in the first region below the polysilicon region. An oxide region is provided on a portion of the first region surface adjacent to the polysilicon region. A third region of the first conductivity type is disposed in the first region adjacent to the second region and below the oxide region. A heavily doped fourth region of the second conductivity type is disposed in the first region adjacent to the third region. The fabrication of the lateral BJT includes the step of forming a polysilicon region on a portion of the first region. Then, the second region is formed by diffusing an impurity from the polysilicon region into the first region.

Abstract: A self-aligned contact process for making an MOS device results in an MOS device with a small and repeatable interconnect size, repeatable interconnect resistance, and reduced source/drain junction capacitance.

Abstract: A CMOS device is provided with a deep collector guard ring. The guard ring is formed by thermally deep diffusing impurities from a poly layer into the surface of a well beneath the poly layer. The guard ring can thus be easily manufactured using CMOS compatible fabrication processes to a depth which is greater than the source and drain regions of the CMOS device.

Abstract: A method of manufacturing a flexible amorphous silicon solar cell includes the steps of: a) coating a PI varnish on a glass substrate; b) imidizing the PI varnish film; c) vacuum-depositing a metal film on the PI film; d) vacuum-depositing an amorphous silicon film on the metal film; e) vacuum-depositing a transparent conducting film on the amorphous silicon film; and f) separating the PI film from the glass substrate. The method also provides for preparing the PI varnish by the steps of: 1) preparing a mixed solution of 60-100% by weight aprotic solvent, and 0-40% by weight aromatic solvent; 2) adding into the mixed solution in a mole ratio of 1:9 two aromatic diamines; and 3) further adding in the mixed solution in a mole ratio of 1:5 two aromatic dianhydrides.

Abstract: A method for fabricating simultaneously bipolar and complementary MOS transistors is disclosed. After a gate oxide layer for the MOS transistors is grown, the gate oxide layer is etched to expose an intrinsic base region on a bipolar transistor well and to reduce thicknesses of opposite portions of base oxide layers that face one another on two sides of the intransic base region. Impurity is implanted into the intrinsic base region so as to form an intrinsic base of the bipolar transistor, the intrinsic base having a base portion between the base oxide layers and a base link portion connected to the base portion and disposed underneath the opposite portions of the base oxide layers. A polysilicon layer is then deposited on the gate oxide layer, and an impurity is implanted into the polysilicon layer and is driven through the polysilicon layer by high temperature treatment to form an emitter region on the surface of the base portion of the intransic base.

Abstract: A small and shrinkable EEPROM cell and method of forming such a cell are provided which includes a control gate having a reentrant profile and a side-wall floating gate conforming to that profile. A predetermined portion of the floating gate overlies the source region which accelerates programming speed. The reentrant profile of the floating gate under the control gate accelerates erasing of the cell. Because of the self-aligned structure of the cell, the EEPROM has a small cell area and is insensitive to layer misalignment. Because of its configuration, the EEPROM cell is easily incorporated into an array of like cells sharing a common source region which facilitates "flash" erasing.