Patents by Inventor Weng Chang

Weng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method
    Patent number: 10304835
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Pre-deposition treatment and atomic layer deposition (ALD) process and structures formed thereby
    Patent number: 10297453
    Abstract: Various methods and structures formed by those methods are described. In accordance with a method, a first metal-containing layer is formed on a substrate. A second metal-containing layer is formed on the substrate. A material of the first metal-containing layer is different from a material of the second metal-containing layer. A chlorine-based treatment is performed on the first metal-containing layer and the second metal-containing layer. A third metal-containing layer is deposited on the first metal-containing layer and the second metal-containing layer using Atomic Layer Deposition (ALD).
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Da-Yuan Lee, JoJo Lee, Ming-Hsing Tsai, Hsueh Wen Tsau, Weng Chang, Ying-Chieh Hung, Yi-Hung Lin
  • METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION
    Publication number: 20180308765
    Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer including an amorphous material is formed over the first and second fin elements, where the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer. The amorphous material of the first layer remains amorphous during the performing of the anneal process.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: De-Wei YU, Chia Ping LO, Liang-Gi YAO, Weng CHANG, Yee-Chia YEO, Ziwei FANG
  • SEMICONDUCTOR DEVICE AND SIDEWALL PASSIVATION AND METHOD OF MAKING
    Publication number: 20180308944
    Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Inventors: Mrunal A. KHADERBAD, Hsueh Wen TSAU, Chia-Ching LEE, Da-Yuan LEE, Hsiao-Kuan WEI, Chih-Chang HUNG, Huicheng CHANG, Weng CHANG
  • SYSTEM FOR PRE-DEPOSITION TREATMENT OF A WORK-FUNCTION METAL LAYER
    Publication number: 20180261459
    Abstract: A system for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.
    Type: Application
    Filed: May 15, 2018
    Publication date: September 13, 2018
    Inventors: Cheng-Yen TSAI, Hsin-Yi LEE, Chung-Chiang WU, Da-Yuan LEE, Weng CHANG, Ming-Hsing TSAI
  • Pre-Deposition Treatment and Atomic Layer Deposition (ALD) Process and Structures Formed Thereby
    Publication number: 20180218912
    Abstract: Various methods and structures formed by those methods are described. In accordance with a method, a first metal-containing layer is formed on a substrate. A second metal-containing layer is formed on the substrate. A material of the first metal-containing layer is different from a material of the second metal-containing layer. A chlorine-based treatment is performed on the first metal-containing layer and the second metal-containing layer. A third metal-containing layer is deposited on the first metal-containing layer and the second metal-containing layer using Atomic Layer Deposition (ALD).
    Type: Application
    Filed: March 26, 2018
    Publication date: August 2, 2018
    Inventors: Cheng-Yen Tsai, Da-Yuan Lee, JoJo Lee, Ming-Hsing Tsai, Hsueh Wen Tsau, Weng Chang, Ying-Chieh Hung, Yi-Hung Lin
  • Semiconductor device with sidewall passivation and method of making
    Patent number: 10014382
    Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mrunal A. Khaderbad, Hsueh Wen Tsau, Chia-Ching Lee, Da-Yuan Lee, Hsiao-Kuan Wei, Chih-Chang Hung, Huicheng Chang, Weng Chang
  • Method of semiconductor integrated circuit fabrication
    Patent number: 10008418
    Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chia-Ping Lo, Liang-Gi Yao, Weng Chang, Yee-Chia Yeo, Ziwei Fang
  • Etching Back and Selective Deposition of Metal Gate
    Publication number: 20180175165
    Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.
    Type: Application
    Filed: June 13, 2017
    Publication date: June 21, 2018
    Inventors: Peng-Soon Lim, Cheng-Lung Hung, Mao-Lin Huang, Weng Chang
  • Methods for pre-deposition treatment of a work-function metal layer
    Patent number: 9978601
    Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Yen Tsai, Hsin-Yi Lee, Chung-Chiang Wu, Da-Yuan Lee, Weng Chang, Ming-Hsing Tsai
  • Pre-deposition treatment and atomic layer deposition (ALD) process and structures formed thereby
    Patent number: 9947540
    Abstract: Various methods and structures formed by those methods are described. In accordance with a method, a first metal-containing layer is formed on a substrate. A second metal-containing layer is formed on the substrate. A material of the first metal-containing layer is different from a material of the second metal-containing layer. A chlorine-based treatment is performed on the first metal-containing layer and the second metal-containing layer. A third metal-containing layer is deposited on the first metal-containing layer and the second metal-containing layer using Atomic Layer Deposition (ALD).
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Da-Yuan Lee, JoJo Lee, Ming-Hsing Tsai, Hsueh Wen Tsau, Weng Chang, Ying-Chieh Hung, Yi-Hung Lin
  • METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION
    Publication number: 20180096898
    Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: De-Wei YU, Chia-Ping LO, Liang-Gi YAO, Weng CHANG, Yee-Chia YEO, Ziwei FANG
  • Semiconductor device and manufacturing method thereof
    Patent number: 9761683
    Abstract: A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chou, Chung-Chiang Wu, Da-Yuan Lee, Weng Chang
  • SEMICONDUCTOR DEVICE WITH PROFILED WORK-FUNCTION METAL GATE ELECTRODE AND METHOD OF MAKING
    Publication number: 20170178973
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 22, 2017
    Inventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
  • ATOMIC LAYER DEPOSITION METHODS AND STRUCTURES THEREOF
    Publication number: 20170110324
    Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.
    Type: Application
    Filed: June 24, 2016
    Publication date: April 20, 2017
    Inventors: Cheng-Yen TSAI, Hsin-Yi LEE, Chung-Chiang WU, Da-Yuan LEE, Weng CHANG, Ming-Hsing TSAI
  • Semiconductor device with metal gate structure comprising work-function metal layer and work-fuction adjustment layer
    Patent number: 9590065
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function meta layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Da-Yuan Lee, Kuan-Ting Liu, Hung-Chin Chung, Hsien-Ming Lee, Weng Chang, Syun-Ming Jang, Wei-Jen Lo
  • PRE-DEPOSITION TREATMENT AND ATOMIC LAYER DEPOSITION (ALD) PROCESS AND STRUCTURES FORMED THEREBY
    Publication number: 20170032972
    Abstract: Various methods and structures formed by those methods are described. In accordance with a method, a first metal-containing layer is formed on a substrate. A second metal-containing layer is formed on the substrate. A material of the first metal-containing layer is different from a material of the second metal-containing layer. A chlorine-based treatment is performed on the first metal-containing layer and the second metal-containing layer. A third metal-containing layer is deposited on the first metal-containing layer and the second metal-containing layer using Atomic Layer Deposition (ALD).
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Cheng-Yen Tsai, Da-Yuan Lee, JoJo Lee, Ming-Hsing Tsai, Hsueh Wen Tsau, Weng Chang, Ying-Chieh Hung, Yi-Hung Lin
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160336420
    Abstract: A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: Chun-Yuan CHOU, Chung-Chiang WU, Da-Yuan LEE, Weng CHANG
  • N metal for FinFET and methods of forming
    Patent number: 9293334
    Abstract: An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Kuo, Chung-Liang Cheng, Hsien-Ming Lee, Weng Chang
  • SEMICONDUCTOR DEVICE WITH SIDEWALL PASSIVATION AND METHOD OF MAKING
    Publication number: 20150262827
    Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mrunai A. Khaderbad, Hsueh Wen Tsau, Chia-Ching Lee, Da-Yuan Lee, Hsiao-Kuan Wei, Chih-Chang Hung, Huicheng Chang, Weng Chang