Patents by Inventor Weng Chang

Weng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for patterning a lanthanum containing layer
    Patent number: 10867869
    Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
  • Method of semiconductor integrated circuit fabrication
    Patent number: 10861751
    Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: De-Wei Yu, Chia Ping Lo, Liang-Gi Yao, Weng Chang, Yee-Chia Yeo, Ziwei Fang
  • SEMICONDUCTOR DEVICE WITH PROFILED WORK-FUNCTION METAL GATE ELECTRODE AND METHOD OF MAKING
    Publication number: 20200335404
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Inventors: Da-Yuan LEE, Hung-Chin CHUNG, Hsien-Ming LEE, Kuan-Ting LIU, Syun-Ming JANG, Weng CHANG, Wei-Jen LO
  • Semiconductor device with profiled work-function metal gate electrode and method of making
    Patent number: 10699966
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
  • SEMICONDUCTOR DEVICE WITH SIDEWALL PASSIVATION AND METHOD OF MAKING
    Publication number: 20200119153
    Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Mrunal A. KHADERBAD, Hsueh Wen TSAU, Chia-Ching LEE, Da-Yuan LEE, Hsiao-Kuan WEI, Chih-Chang HUNG, Huicheng CHANG, Weng CHANG
  • Semiconductor Device and Method
    Publication number: 20200119019
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Etching Back and Selective Deposition of Metal Gate
    Publication number: 20200083351
    Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Inventors: Peng-Soon Lim, Cheng-Lung Hung, Mao-Lin Huang, Weng Chang
  • Method for Patterning a Lanthanum Containing Layer
    Publication number: 20200083115
    Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 12, 2020
    Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
  • Methods for Threshold Voltage Tuning and Structure Formed Thereby
    Publication number: 20200083114
    Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Inventors: Zoe Chen, Ching-Hwanq Su, Cheng-Lung Hung, Cheng-Yen Tsai, Da-Yuan Lee, Hsin-Yi Lee, Weng Chang, Wei-Chin Lee
  • METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION
    Publication number: 20200083112
    Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 12, 2020
    Inventors: De-Wei YU, Chia Ping LO, Liang-Gi YAO, Weng CHANG, Yee-Chia YEO, Ziwei FANG
  • Method for Patterning a Lanthanum Containing Layer
    Publication number: 20200006157
    Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
  • Semiconductor device and method
    Patent number: 10510756
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Semiconductor device having gate body and inhibitor film between conductive prelayer over gate body and conductive layer over inhibitor film
    Patent number: 10510854
    Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mrunal A. Khaderbad, Hsueh Wen Tsau, Chia-Ching Lee, Da-Yuan Lee, Hsiao-Kuan Wei, Chih-Chang Hung, Huicheng Chang, Weng Chang
  • Methods for threshold voltage tuning and structures formed thereby
    Patent number: 10510621
    Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zoe Chen, Ching-Hwanq Su, Cheng-Lung Hung, Cheng-Yen Tsai, Da-Yuan Lee, Hsin-Yi Lee, Weng Chang, Wei-Chin Lee
  • Method for patterning a lanthanum containing layer
    Patent number: 10504795
    Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
  • Method of semiconductor integrated circuit fabrication
    Patent number: 10483170
    Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer including an amorphous material is formed over the first and second fin elements, where the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer. The amorphous material of the first layer remains amorphous during the performing of the anneal process.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chia Ping Lo, Liang-Gi Yao, Weng Chang, Yee-Chia Yeo, Ziwei Fang
  • METHODS FOR THRESHOLD VOLTAGE TUNING AND STRUCTURES FORMED THEREBY
    Publication number: 20190318967
    Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zoe Chen, Ching-Hwanq Su, Cheng-Lung Hung, Cheng-Yen Tsai, Da-Yuan Lee, Hsin-Yi Lee, Weng Chang, Wei-Chin Lee
  • METHOD FOR PATTERNING A LANTHANUM CONTAINING LAYER
    Publication number: 20190304846
    Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Yu LEE, Huicheng CHANG, Che-Hao CHANG, Ching-Hwanq SU, Weng CHANG, Xiong-Fei YU
  • Semiconductor device and method
    Patent number: 10304835
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Pre-deposition treatment and atomic layer deposition (ALD) process and structures formed thereby
    Patent number: 10297453
    Abstract: Various methods and structures formed by those methods are described. In accordance with a method, a first metal-containing layer is formed on a substrate. A second metal-containing layer is formed on the substrate. A material of the first metal-containing layer is different from a material of the second metal-containing layer. A chlorine-based treatment is performed on the first metal-containing layer and the second metal-containing layer. A third metal-containing layer is deposited on the first metal-containing layer and the second metal-containing layer using Atomic Layer Deposition (ALD).
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Da-Yuan Lee, JoJo Lee, Ming-Hsing Tsai, Hsueh Wen Tsau, Weng Chang, Ying-Chieh Hung, Yi-Hung Lin