Abstract: Methods and apparatuses for planarizing microelectronic substrate assemblies on fixed-abrasive polishing pads with non-abrasive lubricating planarizing solutions. One aspect of the invention is to deposit a lubricating planarizing solution without abrasive particles onto a fixed-abrasive polishing pad having a body, a planarizing surface on the body, and a plurality of abrasive particles fixedly attached to the body at the planarizing surface. The front face of a substrate assembly is pressed against the lubricating planarizing solution and at least a portion of the fixed abrasive particles on the planarizing surface of the polishing pad. At least one of the polishing pad or the substrate assembly is then moved with respect to the other to impart relative motion therebetween. As the substrate assembly moves relative to the polishing pad, regions of the front face are separated from the abrasive particles in the polishing pad by a lubricant-additive in the lubricating planarizing solution.

Abstract: An organic acid/fluoride-containing solution etchant having high selectivity for BPSG to TEOS. In an exemplary situation, a TEOS layer may be used to prevent contamination of other components in a semiconductor device by the boron and phosphorous in a layer of BPSG deposited over the TEOS layer. The etchant of the present invention may be used to etch desired areas in the BPSG layer, wherein the high selectivity for BPSG to TEOS of etchant would result in the TEOS layer acting as an etch stop. A second etch with a known etchant may be utilized to etch the TEOS layer. The known etchant for the second etch can be less aggressive and, thus, not damage the components underlying the TEOS layer.

Abstract: In one aspect, the invention encompasses a semiconductor processing method. Two silicon-comprising masses are provided. A first of the two masses comprises a higher dopant concentration than a second of the two masses. The two masses are exposed to common conditions which etch the second mass faster than the first mass. In another aspect, the invention encompasses another embodiment semiconductor processing method. A substrate is provided. The substrate has at least one doped polysilicon mass formed thereover, and has regions not proximate the at least one doped polysilicon mass. Roughened polysilicon is formed along the at least one doped polysilicon mass and over said regions of the substrate. A dopant concentration in the roughened polysilicon is increased along the at least one doped polysilicon mass relative to any dopant concentration in the roughened polysilicon over said regions of the substrate.

Abstract: A surface having exposed doped silicon dioxide such as BPSG is cleaned with a solution that etches thermal oxide at least one-third as fast as it etches the exposed doped silicon dioxide, resulting in more thorough cleaning with less removal of the exposed doped silicon dioxide. Specific applications to formation of container capacitors are disclosed. Preferred cleaning solutions include about 46 parts ammonium fluoride, about 9.5 parts hydrogen fluoride, and about 8.5 parts ammonium hydroxide in about 100 parts water by weight; and about 670 parts ammonium fluoride and about 3 parts hydrogen fluoride in about 1000 parts water by weight. The latter solution is also useful in cleaning methods in which a refractory metal silicide is exposed to the cleaning solution such as in cleaning prior to spacer formation or prior to a gate stack contact fill, in which case about 670 parts ammonium fluoride and about 1.6 parts hydrogen fluoride in about 1000 parts water is most preferred.

Abstract: The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching inorganic antireflective layers without etching excessive amounts of an underlying oxide.

Abstract: In one aspect, the invention encompasses a semiconductor processing method. Two silicon-comprising masses are provided. A first of the two masses comprises a higher dopant concentration than a second of the two masses. The two masses are exposed to common conditions which etch the second mass faster than the first mass. In another aspect, the invention encompasses another embodiment semiconductor processing method. A substrate is provided. The substrate has at least one doped polysilicon mass formed thereover, and has regions not proximate the at least one doped polysilicon mass. Roughened polysilicon is formed along the at least one doped polysilicon mass and over said regions of the substrate. A dopant concentration in the roughened polysilicon is increased along the at least one doped polysilicon mass relative to any dopant concentration in the roughened polysilicon over said regions of the substrate.

Abstract: The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching inorganic antireflective layers without etching excessive amounts of an underlying oxide. According to one aspect of the present invention, the antireflective layer is selectively etched using an etchant which comprises about 35-40 wt. % NH.sub.4 F and about 0.9-5.0 wt. % H.sub.3 PO.sub.4 in an aqueous solution.

Abstract: In one aspect, the invention includes a method of forming an insulative plug within a substrate, comprising: a) forming a masking layer over the substrate, the masking layer having an opening extending therethrough to expose a portion of the underlying substrate; b) etching the exposed portion of the underlying substrate to form an opening extending into the substrate; c) forming an insulative material within the opening in the substrate, the insulative material within the opening forming an insulative plug within the substrate; d) after forming the insulative material within the opening, removing the masking layer; and e) after removing the masking layer, removing a portion of the substrate to lower an upper surface of the substrate relative to the insulative plug.

Abstract: An improved wet etchant process is provided which has greater selectivity than existing hot phosphoric acid etching processes and which maintains a high etch rate in use. The etchant composition includes a second acid having a boiling point higher than that of the phosphoric acid.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H.sub.2 SO.sub.4, H.sub.3 PO.sub.4, HNO.sub.3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.

Abstract: Disclosed is a process for cleaning silicon surfaces of native oxide films. The process utilizes fluorine containing cleaning materials such as anhydrous hydrofluoric acid to clean the oxide from the surface. A fluorine containing particulate matter which forms on the surface as a result of the fluorine containing cleaning materials is then removed by heating the surface to a high temperature. The process is conducted in a non-oxidizing ambient and is preferably conducted in a cluster tool so that the heating step can take place in the same chamber of the cluster tool as later metal deposition step.

Abstract: A surface having exposed doped silicon dioxide such as BPSG is cleaned with a vapor phase solution that etches thermal oxide at least one-third as fast as it etches the exposed doped silicon dioxide, resulting in more thorough cleaning with less removal of the exposed doped silicon dioxide. Specific applications to formation of container capacitors are disclosed. Preferred cleaning vapor phase solutions include about 1% water, about 5% hydrogen fluoride, and about 5% ammonias. The vapor phase solution is also useful in cleaning methods in which a refractory metal silicide is exposed to the cleaning vapor phase solution such as in cleaning prior to spacer formation or prior to a gate stack contact fill, in which case about 500 PPMV water, about 2% hydrogen fluoride, and about 2% ammonia is most preferred.

Abstract: The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching inorganic antireflective layers without etching excessive amounts of an underlying oxide. According to one aspect of the present invention, the antireflective layer is selectively etched using an etchant which comprises about 35-40 wt. % NH.sub.4 F and about 0.9-5.0 wt. % H.sub.3 PO.sub.4 in an aqueous solution.

Abstract: An improved wet etchant process is provided which has greater selectivity than existing hot phosphoric acid etching processes and which maintains a high etch rate in use. The etchant composition includes a second acid having a boiling point higher than that of the phosphoric acid.

Abstract: Disclosed is a process for cleaning silicon surfaces of native oxide films. The process utilizes fluorine containing cleaning materials such as anhydrous hydrofluoric acid to clean the oxide from the surface. A fluorine containing particulate matter which forms on the surface as a result of the fluorine containing cleaning materials is then removed by heating the surface to a high temperature. The process is conducted in a non-oxidizing ambient and is preferably conducted in a cluster tool so that the heating step can take place in the same chamber of the cluster tool as later metal deposition step.

Abstract: A surface having exposed doped silicon dioxide such as BPSG is cleaned with a solution that etches thermal oxide at least one-third as fast as it etches the exposed doped silicon dioxide, resulting in more thorough cleaning with less removal of the exposed doped silicon dioxide. Specific applications to formation of container capacitors are disclosed. Preferred cleaning solutions include about 46 parts ammonium fluoride, about 9.5 parts hydrogen fluoride, and about 8.5 parts ammonium hydroxide in about 100 parts water by weight; and about 670 parts ammonium fluoride and about 3 parts hydrogen fluoride in about 1000 parts water by weight. The latter solution is also useful in cleaning methods in which a refractory metal silicide is exposed to the cleaning solution such as in cleaning prior to spacer formation or prior to a gate stack contact fill, in which case about 670 parts ammonium fluoride and about 1.6 parts hydrogen fluoride in about 1000 parts water is most preferred.

Abstract: A surface having exposed doped silicon dioxide such as BPSG is cleaned with a vapor phase solution that etches thermal oxide at least one-third as fast as it etches the exposed doped silicon dioxide, resulting in more thorough cleaning with less removal of the exposed doped silicon dioxide. Specific applications to formation of container capacitors are disclosed. Preferred cleaning vapor phase solutions include about 1% water, about 5% hydrogen fluoride, and about 5% ammonia. The vapor phase solution is also useful in cleaning methods in which a refractory metal silicide is exposed to the cleaning vapor phase solution such as in cleaning prior to spacer formation or prior to a gate stack contact fill, in which case about 500 PPMV water, about 2% hydrogen fluoride, and about 2% ammonia is most preferred.