Patents by Inventor Wilbur G. Catabay
Wilbur G. Catabay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
Patent number: 8043968Abstract: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.Type: GrantFiled: April 20, 2010Date of Patent: October 25, 2011Assignee: LSI Logic CorporationInventors: Hao Cui, Peter A. Burke, Wilbur G. Catabay -
DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
Publication number: 20100200993Abstract: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.Type: ApplicationFiled: April 20, 2010Publication date: August 12, 2010Applicant: LSI CORPORATIONInventors: Hao Cui, Peter A. Burke, Wilbur G. Catabay -
Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
Patent number: 7728433Abstract: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.Type: GrantFiled: April 17, 2007Date of Patent: June 1, 2010Assignee: LSI CorporationInventors: Hao Cui, Peter A. Burke, Wilbur G. Catabay -
Patent number: 7675177Abstract: A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.Type: GrantFiled: March 7, 2005Date of Patent: March 9, 2010Assignee: LSI CorporationInventors: Hongqiang Lu, Byung-Sung Kwak, Wilbur G. Catabay
-
Patent number: 7646077Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.Type: GrantFiled: August 13, 2008Date of Patent: January 12, 2010Assignee: LSI CorporationInventors: Hong-Qiang Lu, Peter A. Burke, Wilbur G. Catabay
-
DIELECTRIC BARRIER FILMS FOR USE AS COPPER BARRIER LAYERS IN SEMICONDUCTOR TRENCH AND VIA STRUCTURES
Publication number: 20080303155Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.Type: ApplicationFiled: August 13, 2008Publication date: December 11, 2008Applicant: LSI CORPORATIONInventors: Hong-Qiang LU, Peter A. BURKE, Wilbur G. CATABAY -
Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures
Patent number: 7427563Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.Type: GrantFiled: May 16, 2005Date of Patent: September 23, 2008Assignee: LSI CorporationInventors: Hong-Qiang Lu, Peter A. Burke, Wilbur G. Catabay -
Patent number: 7413984Abstract: Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate with a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum is formed on the first barrier layer. A copper seed layer is formed on the second barrier layer and implanted with barrier ions and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization.Type: GrantFiled: April 10, 2007Date of Patent: August 19, 2008Assignee: LSI CorporationInventors: Wilbur G. Catabay, Zhihai Wang, Ping Li
-
Patent number: 7393780Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.Type: GrantFiled: May 4, 2006Date of Patent: July 1, 2008Assignee: LSI CorporationInventors: Hong-Qiang Lu, Wei-Jen Hsia, Wilbur G. Catabay
-
Patent number: 7312127Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.Type: GrantFiled: March 23, 2006Date of Patent: December 25, 2007Assignee: LSI CorporationInventors: Wai Lo, Verne Hornback, Wilbur G. Catabay, Wei-Jen Hsia, Sey-Shing Sun
-
Patent number: 7285145Abstract: Embodiments of the invention include a method for electro chemical mechanical polishing of a substrate. The process includes flowing an electro chemical mechanical polishing (ECMP) slurry having a high viscosity with a polishing agent over a portion of the substrate. Electrical current is passed through the slurry and substrate. The electrical current, in conjunction with the abrading action of the slurry as it flows over the surface of the substrate, serves to remove at least a portion of the metal layer from the substrate. The invention also includes various slurry embodiments.Type: GrantFiled: December 7, 2004Date of Patent: October 23, 2007Assignee: LSI CorporationInventors: Mei Zhu, Wilbur G. Catabay
-
Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
Patent number: 7276441Abstract: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.Type: GrantFiled: April 15, 2003Date of Patent: October 2, 2007Assignee: LSI Logic CorporationInventors: Hao Cui, Peter A. Burke, Wilbur G. Catabay -
Patent number: 7259462Abstract: An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.Type: GrantFiled: May 22, 2006Date of Patent: August 21, 2007Assignee: LSI CorporationInventors: Wai Lo, Hong Lin, Shiqun Gu, Wilbur G. Catabay, Zhihai Wang, Wei-Jen Hsia
-
Patent number: 7229923Abstract: Methods for forming robust copper structures include steps for providing a substrate with an insulating layer with openings formed therein. At least two barrier layers are then formed followed by the deposition of a copper seed layer which is annealed. Bulk copper deposition of copper and planarization can follow. In one approach the seed layer is implanted with suitable materials forming an implanted seed layer upon which a bulk layer of conductive material is formed and annealed to form a final barrier layer. In another approach, a barrier layer is formed between two seed layers which forms a base for bulk copper deposition. Another method involves forming a first barrier layer and forming a copper seed layer thereon. The seed layer being implanted with a barrier material (e.g. palladium, chromium, tantalum, magnesium, and molybdenum or other suitable materials) and then bulk deposition of copper-containing material is performed followed by annealing.Type: GrantFiled: February 3, 2004Date of Patent: June 12, 2007Assignee: LSI CorporationInventors: Wilbur G. Catabay, Zhihai Wang, Ping Li
-
Patent number: 7220362Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.Type: GrantFiled: January 23, 2006Date of Patent: May 22, 2007Assignee: LSI CorporationInventors: Wilbur G. Catabay, Wei-Jen Hsia, Hao Cui
-
Patent number: 7081406Abstract: An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.Type: GrantFiled: August 10, 2004Date of Patent: July 25, 2006Assignee: LSI Logic CorporationInventors: Wai Lo, Hong Lin, Shiqun Gu, Wilbur G. Catabay, Zhihai Wang, Wei-Jen Hsia
-
Patent number: 7071094Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.Type: GrantFiled: July 16, 2004Date of Patent: July 4, 2006Assignee: LSI Logic CorporationInventors: Hong-Qiang Lu, Wei-Jen Hsia, Wilbur G. Catabay
-
Patent number: 7064062Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.Type: GrantFiled: December 16, 2003Date of Patent: June 20, 2006Assignee: LSI Logic CorporationInventors: Wai Lo, Verne Hornback, Wilbur G. Catabay, Wei-Jen Hsia, Sey-Shing Sun
-
Patent number: 7029591Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.Type: GrantFiled: April 23, 2003Date of Patent: April 18, 2006Assignee: LSI Logic CorporationInventors: Wilbur G. Catabay, Wei-Jen Hsia, Hao Cui
-
Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures
Patent number: 6939800Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.Type: GrantFiled: December 16, 2002Date of Patent: September 6, 2005Assignee: LSI Logic CorporationInventors: Hong-Qiang Lu, Peter A. Burke, Wilbur G. Catabay