Abstract: A method for planarizing a surface of an electrically conductive layer on a substrate, where the surface of the electrically conductive layer has relatively high features and relatively low features. A viscous material is applied to the surface of the electrically conductive layer, whereby at least the relatively low features are covered by the viscous material. The substrate is immersed in an electrically conductive solution. An electrical potential is applied between the electrically conductive layer and an electrode within the electrically conductive solution, whereby reaction kinetics favor erosion of the electrically conductive layer. The electrically conductive solution is agitated, thereby selectively uncovering the viscous material from at least features that are relatively high, and thereby preferentially planarizing at least the features that are relatively high.

Abstract: A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer of densified dielectric material over the remainder of the underlying layer of low k dielectric material, forming a second layer of low k dielectric material over the layer of densified dielectric material, and treating this second layer of low k dielectric material to form a second layer of densified dielectric material over the second layer of low k dielectric material. The layer or layers of densified dielectric material formed from the low k dielectric material provide mechanical support and can then function as etch stop and mask layers for the formation of vias and/or trenches.

Abstract: A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.

Abstract: A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.

Abstract: A three step process for planarizing an integrated circuit structure comprising one or more dielectric layers having trench and/or via openings therein lined with a layer of electrically conductive barrier liner material and filled with copper filler material. Sufficient excess copper (formed over the barrier liner portions on the top surface of the dielectric layer) is removed in an initial chemical mechanical polish (CMP) step to provide a planarized copper layer with a global planarity of about 20 nm to about 30 nm. The remainder of the excess copper over the portion of the barrier liner material lying on the top surface of the dielectric layer is then removed by electropolishing the structure, in a second step, until all of the excess copper over the portion of the barrier liner material lying on the top surface of the dielectric layer is removed.

Abstract: Embodiments of the invention include a method for forming copper interconnect structure. The method involves providing a substrate having a copper conductive layer formed thereon. An insulating layer having openings is formed on the conductive layer so that the openings expose portions of the underlying conductive layer at the bottom of the openings. A barrier layer is formed on the surface of the substrate. A portion of the barrier layer is removed at the bottom of the opening to expose the underlying conductive layer. A copper plug is formed in the opening such that the bottom of the plug is in contact with the exposed conductive layer. The substrate can be subjected to further processing if desired. The invention also includes a copper interconnect structure having increased resistance to electromigration.

Abstract: Embodiments of the invention include a method for electro chemical mechanical polishing of a substrate. The process includes flowing an electro chemical mechanical polishing (ECMP) slurry having a high viscosity with a polishing agent over a portion of the substrate. Electrical current is passed through the slurry and substrate. The electrical current, in conjunction with the abrading action of the slurry as it flows over the surface of the substrate, serves to remove at least a portion of the metal layer from the substrate. The invention also includes various slurry embodiments.

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

Abstract: A method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit, where the dielectric structures have an upper level. The copper layer is planarized to be no higher than the upper level of the dielectric structures, without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer, without the capping layer forming over any of the dielectric structures.

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

Abstract: A composite layer of low k silicon oxide dielectric material is formed on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon. The composite layer of low k silicon oxide dielectric material exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines, deposition rates in other regions comparable to standard k silicon oxide, and reduced via poisoning characteristics. The composite layer of low k silicon oxide dielectric material is formed by depositing, in high aspect ratio regions between closely spaced apart metal lines, a first layer of low k silicon oxide dielectric material exhibiting void-free deposition properties until the resulting deposition of low k silicon oxide dielectric material reaches the level of the top of the metal lines on the oxide layer.

Abstract: A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps.

Abstract: A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer of densified dielectric material over the remainder of the underlying layer of low k dielectric material, forming a second layer of low k dielectric material over the layer of densified dielectric material, and treating this second layer of low k dielectric material to form a second layer of densified dielectric material over the second layer of low k dielectric material. The layer or layers of densified dielectric material formed from the low k dielectric material provide mechanical support and can then function as etch stop and mask layers for the formation of vias and/or trenches.

Abstract: A method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit, where the dielectric structures have an upper level. The copper layer is planarized to be no higher than the upper level of the dielectric structures, without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer, without the capping layer forming over any of the dielectric structures.

Abstract: Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate in a processing chamber, the substrate having a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer is formed on the first barrier layer. The second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum. A copper seed layer is formed on the second barrier layer and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization.

Abstract: The present invention is directed to a semiconductor structure including a semiconductor substrate having at least one overlying layer formed thereon. The at least one overlying layer including at least one layer of dielectric material. The at least one layer of dielectric material including a protected region having a first dielectric constant and another porous region having a second dielectric constant wherein the value for the second dielectric constant is less than the first dielectric constant. The porous region having been formed by the implantation of a porosity inducing material into the porous region and subsequent annealing. A method for forming such structures is also included.

Abstract: A method of processing a substrate, where the substrate is transferred from an ambient environment into a clean environment. The substrate is heated to at least a first temperature within the clean environment, and then maintained at no less than the first temperature within the clean environment. The substrate is selectively transferred within the clean environment to more than one processing chambers, and processed in the more than one processing chambers. The substrate is transferred from the clean environment into the ambient environment.

Abstract: An integrated circuit structure is disclosed wherein the capacitance between nearby conductive portions may be lowered using carbon-containing low k silicon oxide dielectric material, without contributing to the problem of via poisoning, by careful control of the carbon content of the dielectric material in two regions of the integrated circuit structure. The first region comprises the region between adjacent raised conductive lines formed over an underlying insulation layer, where undesirable capacitance may be formed horizontally between such adjacent conductive lines, while the second region comprises the region above the raised conductive lines where vias are normally formed extending upward from the raised conductive lines through the dielectric layer to an overlying layer of metal interconnects.

Abstract: An integrated circuit including an electrically conductive interconnect having a first barrier layer consisting essentially of a diamond film. A seed layer consisting essentially of copper is disposed adjacent the first barrier layer. A conductive layer consisting essentially of copper is disposed adjacent the seed layer.