Patents by Inventor Wilbur G. Catabay

Wilbur G. Catabay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6727177
    Abstract: Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method involves providing a substrate having an insulating layer with an opening therein configured to receive an inlaid conducting structure. A copper seed layer is formed on the insulating layer and in the opening. The seed layer is implanted with barrier material ions to form an implanted seed layer. Upon the implanted seed layer is formed a bulk copper-containing layer. The substrate is then annealed so that barrier material ions migrate through the seed layer to an interface between the seed layer and the insulating layer to form a final barrier layer. The barrier material can include palladium, chromium, tantalum, magnesium, and molybdenum.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: April 27, 2004
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Zhihai Wang, Ping Li
  • Patent number: 6686272
    Abstract: The present invention is directed to a silicon carbide anti-reflective coating (ARC) and a silicon oxycarbide ARC. Another embodiment is directed to a silicon oxycarbide ARC that is treated with oxygen plasma. The invention includes method embodiments for forming silicon carbide layers and silicon oxycarbide layers as ARC's on a semiconductor substrate surface. Particularly, the methods include introducing methyl silane materials into a process chamber where they are ignited as plasma and deposited onto the substrate surface as silicon carbide. Another method includes introducing methyl silane precursor materials with an inert carrier gas into the process chamber with oxygen. These materials are ignited into a plasma, and silicon oxycarbide material is deposited onto the substrate. By regulating the oxygen flow rate, the optical properties of the silicon oxycarbide layer can be adjusted. In another embodiment, the silicon oxycarbide layer can be treated with oxygen plasma.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: February 3, 2004
    Assignee: LSI Logic Corporation
    Inventors: Sang-Yun Lee, Masaichi Eda, Hongqiang Lu, Wei-Jen Hsia, Wilbur G. Catabay, Hiroaki Takikawa, Yongbae Kim
  • Publication number: 20040009668
    Abstract: A three step process for planarizing an integrated circuit structure comprising one or more dielectric layers having trench and/or via openings therein lined with a layer of electrically conductive barrier liner material and filled with copper filler material.
    Type: Application
    Filed: July 7, 2003
    Publication date: January 15, 2004
    Inventors: Wilbur G. Catabay, Richard Schinella, Zhihai Wang, Wei-Jen Hsia
  • Publication number: 20030207594
    Abstract: A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer of densified dielectric material over the remainder of the underlying layer of low k dielectric material, forming a second layer of low k dielectric material over the layer of densified dielectric material, and treating this second layer of low k dielectric material to form a second layer of densified dielectric material over the second layer of low k dielectric material. The layer or layers of densified dielectric material formed from the low k dielectric material provide mechanical support and can then function as etch stop and mask layers for the formation of vias and/or trenches.
    Type: Application
    Filed: April 24, 2003
    Publication date: November 6, 2003
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia
  • Patent number: 6613665
    Abstract: A process is disclosed for forming an integrated circuit structure characterized by formation of a combined dielectric layer and antireflective coating layer. The process comprises forming a layer of dielectric material over an integrated circuit structure, and treating the surface of the layer of dielectric material to form an antireflective coating (ARC) surface therein. When a layer of photoresist is then formed over the ARC surface, and the layer of photoresist is exposed to a pattern of radiation, the ARC surface improves the accuracy of the replication, in the photoresist layer, of the pattern of radiation. Preferably, the surface of the dielectric layer is treated with a plasma comprising ions of elements and/or compounds to form the ARC surface.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: September 2, 2003
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia
  • Publication number: 20030084587
    Abstract: An apparatus for performing contaminant sensitive processing on a substrate. A substrate load chamber receives the substrate from an ambient contaminant laden environment, and isolates the substrate from the ambient contaminant laden environment. The substrate load chamber further forms a first environment of intermediate cleanliness around the substrate. A substrate pass through chamber receives the substrate from the substrate load chamber, and isolates the substrate from the intermediate cleanliness of the first environment of the substrate load chamber. The substrate pass through chamber further forms a second environment of high cleanliness around the substrate. A substrate transfer chamber receives the substrate from the substrate pass through chamber, and isolates the substrate from the high cleanliness of the second environment of the substrate pass through chamber.
    Type: Application
    Filed: December 18, 2002
    Publication date: May 8, 2003
    Applicant: LSI Logic Corporation
    Inventors: Kiran Kumar, Zhihai Wang, Rudy Rios, Wilbur G. Catabay, Richard D. Schinella
  • Publication number: 20030064593
    Abstract: A method for creating a highly reflective surface on an electroplated conduction layer. A barrier layer is deposited on a substrate using a self ionized plasma deposition process. The barrier layer has a thickness of no more than about one hundred angstroms. An adhesion layer is deposited on the barrier layer, using a self ionized plasma deposition process. A seed layer is deposited on the adhesion layer, also using a self ionized plasma deposition process, at a bias of no les than about one hundred and fifty watts. The combination of the barrier layer, adhesion layer, and seed layer is at times referred to herein as the barrier seed layer. The conduction layer is electroplated on the seed layer, thereby forming the highly reflective surface on the conduction layer, where the highly reflective surface has a reflectance of greater than about seventy percent.
    Type: Application
    Filed: October 10, 2002
    Publication date: April 3, 2003
    Applicant: LSI Logic Corporation
    Inventors: Kiran Kumar, Zhihai Wang, Wilbur G. Catabay
  • Publication number: 20030064588
    Abstract: A method of forming an electrically conductive interconnect on a substrate. An interconnection feature is formed on the substrate, and a first barrier layer is deposited on the substrate. The first barrier layer consists essentially of a diamond film. A seed layer consisting essentially of copper is deposited on the substrate, and a conductive layer consisting essentially of copper is deposited on the substrate. Thus, by using a diamond film as the barrier layer, diffusion of the copper from the conductive layer into the material of the substrate is substantially reduced and preferably eliminated.
    Type: Application
    Filed: September 9, 2002
    Publication date: April 3, 2003
    Applicant: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Zhihai Wang
  • Patent number: 6537896
    Abstract: A process for forming a non-porous dielectric diffusion barrier layer on etched via and trench sidewall surfaces in a layer of porous low k dielectric material comprises exposing such etched surfaces to a plasma formed from one or more gases such as, for example, O2; H2; Ar; He; SiH4; NH3; N2; CHxFy, where x=1-3 and y=4-y; H2O; and mixtures of same, for a period of time sufficient to form from about 1 nanometer (nm) to about 20 nm of the non-porous dielectric diffusion barrier layer which prevents adsorption of moisture and other process gases into the layer of porous low k dielectric material, and prevents degassing from the porous low k dielectric material during subsequent processing.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: March 25, 2003
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia
  • Patent number: 6528423
    Abstract: A process for forming an integrated circuit structure characterized by formation of an improved barrier layer for protection against migration of copper from a copper-containing layer into low k dielectric material while mitigating undesired increase in dielectric constant and mitigating undesirable interference by materials in the barrier layer with subsequent photolithography.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: March 4, 2003
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia
  • Patent number: 6518193
    Abstract: An apparatus for performing contaminant sensitive processing on a substrate. A substrate load chamber receives the substrate from an ambient contaminant laden environment, and isolates the substrate from the ambient contaminant laden environment. The substrate load chamber further forms a first environment of intermediate cleanliness around the substrate. A substrate pass through chamber receives the substrate from the substrate load chamber, and isolates the substrate from the intermediate cleanliness of the first environment of the substrate load chamber. The substrate pass through chamber further forms a second environment of high cleanliness around the substrate. A substrate transfer chamber receives the substrate from the substrate pass through chamber, and isolates the substrate from the high cleanliness of the second environment of the substrate pass through chamber.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: February 11, 2003
    Assignee: LSI Logic Corporation
    Inventors: Kiran Kumar, Zhihai Wang, Rudy Rios, Wilbur G. Catabay, Richard D. Schinella
  • Patent number: 6503840
    Abstract: A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: January 7, 2003
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Hong-Qiang Lu, Yong-Bae Kim, Kiran Kumar, Kai Zhang, Richard Schinella, Philippe Schoenborn
  • Patent number: 6492731
    Abstract: A composite layer of low k dielectric material for integrated circuit structures comprising a thick lower conformal barrier layer of low k dielectric material, a low k center layer of carbon-doped silicon oxide dielectric material having good gap filling capabilities, and a thick upper conformal barrier layer of low k dielectric material. The thick lower conformal barrier layer of low k dielectric material protects the lower surface of the main low k dielectric layer and also protects against misaligned vias entering the main low k dielectric material below the height of the metal line without raising the capacitance of the structure as would a lower barrier layer of non-low k dielectric material.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: December 10, 2002
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Kai Zhang
  • Publication number: 20020164877
    Abstract: A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus.
    Type: Application
    Filed: May 2, 2001
    Publication date: November 7, 2002
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Hong-Qiang Lu, Yong-Bae Kim, Kiran Kumar, Kai Zhang, Richard Schinella, Philippe Schoenborn
  • Patent number: 6472314
    Abstract: A method of forming an electrically conductive interconnect on a substrate. An interconnection feature is formed on the substrate, and a first barrier layer is deposited on the substrate. The first barrier layer consists essentially of a diamond film. A seed layer consisting essentially of copper is deposited on the substrate, and a conductive layer consisting essentially of copper is deposited on the substrate. Thus, by using a diamond film as the barrier layer, diffusion of the copper from the conductive layer into the material of the substrate is substantially reduced and preferably eliminated.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: October 29, 2002
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Zhihai Wang
  • Publication number: 20020135040
    Abstract: A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps.
    Type: Application
    Filed: May 21, 2002
    Publication date: September 26, 2002
    Inventors: Weidan Li, Wilbur G. Catabay, Wei-Jen Hsia
  • Publication number: 20020123243
    Abstract: A composite layer of low k silicon oxide dielectric material is formed on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon. The composite layer of low k silicon oxide dielectric material exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines, deposition rates in other regions comparable to standard k silicon oxide, and reduced via poisoning characteristics. The composite layer of low k silicon oxide dielectric material is formed by depositing, in high aspect ratio regions between closely spaced apart metal lines, a first layer of low k silicon oxide dielectric material exhibiting void-free deposition properties until the resulting deposition of low k silicon oxide dielectric material reaches the level of the top of the metal lines on the oxide layer.
    Type: Application
    Filed: March 15, 2002
    Publication date: September 5, 2002
    Inventors: Wilbur G. Catabay, Richard Schinella
  • Patent number: 6423630
    Abstract: A process is disclosed for forming low k dielectric material between and over a plurality of spaced apart metal lines previously formed over a dielectric layer of an integrated circuit structure. The steps include: depositing, over and between the plurality of metal lines, a layer of a first low k dielectric material resistant to via poisoning; then planarizing the layer of first low k dielectric material sufficiently to open voids formed in. the first low k dielectric material between the metal lines; then depositing, over the layer of first low k dielectric material and into the opened voids, a layer of second low k dielectric material capable of filling the opened voids in the layer of first low k dielectric material; and then depositing a layer of a third low k dielectric material resistant to via poisoning over the first low k dielectric material and the voids filled with the second low k dielectric material.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: July 23, 2002
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Dung-Ching Perng
  • Patent number: 6423628
    Abstract: A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: July 23, 2002
    Assignee: LSI Logic Corporation
    Inventors: Weidan Li, Wilbur G. Catabay, Wei-Jen Hsia
  • Patent number: 6420277
    Abstract: A process is disclosed which inhibits cracking of the layer of low k silicon oxide dielectric material on an integrated circuit structure during subsequent processing of the layer of low k silicon oxide dielectric material. The process comprises: forming a layer of low k silicon oxide dielectric material on an integrated circuit structure on a semiconductor substrate, and forming over the layer of low k silicon oxide dielectric material a capping layer of dielectric material having: a dielectric constant not exceeding about 4, a thickness of at least about 300 nm, and a compressive stress of at least about 3×109 dynes/cm2. In a preferred embodiment, the capping layer comprises silicon oxide formed by reaction of silane and N2O in a PECVD process carried out within a pressure range of from about 600 milliTorr to about 1000 milliTorr; and a temperature range of from about 300° C. to about 400° C.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: July 16, 2002
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Hong Qiang