Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate.

Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

Abstract: A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor 124 comprising at least body region 127 and diffusion regions 132; buried interconnect plane 122 optionally self-aligned to diffusion regions 132 and in contact with body region 127; isolation oxide region 118 between diffusion regions 132 and buried interconnect plane 122; and buried oxide layer 104 present beneath buried interconnect plane 122.

Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

Abstract: A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor 124 comprising at least body region 127 and diffusion regions 132; buried interconnect plane 122 optionally self-aligned to diffusion regions 132 and in contact with body region 127; isolation oxide region 118 between diffusion regions 132 and buried interconnect plane 122; and buried oxide layer 104 present beneath buried interconnect plane 122.

Abstract: An SOI multiple FET structure is provided that comprises a substrate having a substrate layer on an insulator layer. The SOI multiple FET structure includes distal diffusion regions in the substrate layer and a central diffusion region in the substrate layer. The central diffusion region has a width and extends from a surface of the substrate layer downward into contact with the insulator layer along a portion of the width and extends only partially into the substrate layer along another portion of the width. The SOI multiple FET structure also includes a pair of gates on the surface of the substrate layer each overlapping one of the distal diffusion regions and the central diffusion region; and a pair of body regions in the substrate layer each under one of the gates for forming a channel between the one of the distal diffusion regions and the central diffusion region. The body regions are in electrical communication under the another portion of the width of the central diffusion region.

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate.

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate.

Abstract: A decoupling capacitor and methods for forming the same are provided. In a first aspect, the decoupling capacitor is formed during a process for forming first and second type FETs on a common substrate that comprises a plurality of implant steps for doping channels and diffusions of the first and second type FETs. In a second aspect, a method is provided for forming the novel decoupling capacitor that includes the steps of forming a mandrel layer on a substrate, including forming openings in the mandrel layer and disposing a first type dopant into the substrate through the openings. Thereafter, an epitaxial layer is formed in the openings on the substrate, an insulator layer is formed in the openings on the epitaxial layer and a gate is formed in the openings on the insulator layer. The mandrel layer is removed and the first type dopant is disposed into the substrate abutting the first type dopant in the substrate that was disposed through the openings.

Abstract: A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor 124 comprising at least body region 127 and diffusion regions 132; buried interconnect plane 122 optionally self-aligned to diffusion regions 132 and in contact with body region 127; isolation oxide region 118 between diffusion regions 132 and buried interconnect plane 122; and buried oxide layer 104 present beneath buried interconnect plane 122.

Abstract: A method of fabricating a semiconductor device comprising: forming a trench on the face of a silicon substrate of a first conductivity type; depositing a conformal silicon layer of a second conductivity type into the trench; etching away the silicon layer of a second conductivity type selectively to leave portions of the silicon layer in the trench; annealing to drive dopant from the portions of the silicon layer through the walls of the trench into adjacent areas of the silicon substrate; and forming a gate structure in the trench, and source and drain diffusion regions in said silicon substrate on opposing sides of said gate structure.

Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

Abstract: Method of forming a film for a semiconductor device in which a source material comprising a deuterated species is provided during formation of the film.

Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

Abstract: It has been found that by administering secoisolariciresinol ?2,3-bis(3-methyl-4-hydroxybenzyl)butane-1,4-diol! from flaxseed in substantially pure form to a human or non-human animal, lupus nephritis can be controlled. The secoisolariciresinol (Seco) may be used per se or in the form of secoisolariciresinol diglucoside (SDG). Both compounds may be extracted from flaxseed and the SDG converts to Seco in the gut of a human or animal.

Abstract: In use with a photosensitive web roll located inside a light-tight container having an exit slot through which the web is withdrawable, a flexible enclosure is provided for light-shielding a leading end portion of the web extending from the roll through the slot and outside the container. The enclosure comprises a flexible, substantially rectangular, opaque sleeve adapted to enclose the web end portion. The sleeve includes opposing top and bottom walls disposed in adjacent, registered, facing relationship and extending between front and rear ends and opposite lateral sides thereof. The walls are light-tightly joined together along their front ends and lateral sides, but are left unjoined and separable along their rear ends to provide an opening therebetween through which the web end portion can be inserted into the sleeve toward the joined front ends.