Abstract: An imaging apparatus comprising: A spatial light modulator (30) operable to receive incident light (34) representing an incident light image and to intensity modulate said incident light to form spatially modulated (38) light; and an image capture device (42) operable to receive said spatially modulated light and to detect an intensity value for different portions of said spatially modulated light to form a modulated light image therefrom; wherein said spatial light modulator attenuates different parts of said incident light by different proportions such that intensity values of said incident light image are given by a combination of intensity values of said modulated light image captured by said image capture device and data representing proportions of attenuation applied to corresponding parts of said incident light image by said spatial light modulator.

Abstract: A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows through the coil passes through an electron-hole generation region. Charged particles in the electron-hole generation region come under the influence of the magnetic field, and generate eddy currents whose magnitudes depend on whether light is absent or present. The eddy currents generate a magnetic field that opposes the magnetic field generated by current flowing through the coil.

Abstract: Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.

Abstract: A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.

Abstract: A semiconductor capacitor with large area plates and a small footprint is formed on a semiconductor wafer by forming an opening in the wafer, depositing a first metal atoms through a first shadow mask that lies spaced apart from the wafer to form a first metal layer in the opening, a dielectric layer on the first metal layer, and a second metal atoms through a second shadow mask that lies spaced apart from the wafer to form a second metal layer on the dielectric layer.

Abstract: A method for calculating power for a data storage system. The method includes: measuring power requirement for each one of a plurality of components for use in one of a plurality of possible system configurations; storing the measured power requirement in a table; entering into the table a specified one of the possible system configurations to obtain the power requirement for such one of the specified system configurations; calculating from the table the total power expected for the specified system configuration; presenting the calculated power to a user; determining whether the calculated power is acceptable or unacceptable to the user; and if determined to be unacceptable, entering into the table a new system configuration.

Abstract: The present invention relates to methods to identify one or more conditions in a subject. In particular, it relates to methods of identifying a condition such as cancer, which changes a lipid profile in a keratin-containing component of a subject, the changes to the lipid profile being determined by techniques such as chromatography and mass spectrometry.

Abstract: An integrated circuit die system comprises a first integrated circuit die, a second integrated circuit die and a transformer formed on a dielectric (e.g., quartz) substrate and electrically connected between the first integrated circuit die and the second integrated circuit die to provide galvanic isolation therebetween.

Abstract: An orientation sensor includes a measure of ferrofluid that moves as the orientation sensor moves. The movement of the ferrofluid, which lies over a number of coils, alters the magnetic permeability of the flux path around each coil. The orientation sensor determines a change in orientation by measuring a change in the voltage across each coil. The voltage across each coil changes as the inductance changes which, in turn, changes as the magnetic permeability of the flux path changes.

Abstract: An on-chip inductor structure is formed as part of an integrated circuit structure. The integrate circuit structure includes a semiconductor substrate having a top side and a back side, integrated circuit elements formed on the top side of the substrate, a conductive interconnect structure formed in contact with the integrated circuit elements and a passivation layer formed over the integrated circuit elements. The inductor structure comprises a layer of photoimageable epoxy formed on the passivation layer, a conductive inductor coil formed on the layer of photoimageable epoxy and at least one conductive via that extends from the inductor coil to the interconnect layer to provide electrical connection therebetween. Additionally, a back side trench may be formed in the back side of the semiconductor substrate beneath the inductor coil.

Abstract: A semiconductor wafer that provides galvanic isolation is formed in a very cost efficient manner by attaching a non-conductive wafer to a silicon wafer to form a hybrid wafer, and then simultaneously wet etching a large number of hybrid wafers to form a thin non-conductive wafer that is attached to a thick silicon wafer. After a large number of high-voltage devices have been formed on the thin non-conductive wafer, the thick silicon wafer is thinned or removed so that the hybrid wafer is suitable for packaging.

Abstract: A silicon-on-insulator (SOI) wafer is formed to have through-the-wafer contacts, and trench based interconnect structures on the back side of the SOI wafer that electrically connect the through-the-wafer contacts. In addition, selected ones of the through-the-wafer contacts bias the bodies of the MOS transistors.

Abstract: An interdigitated semiconductor capacitor with a large number of plates and a capacitance in the micro-farad range is formed on a wafer with only a single lithography step by depositing each odd layer of metal through a first shadow mask that lies spaced apart from the wafer, and each even layer of metal through a second shadow mask that lies spaced apart from the wafer.

Abstract: A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.

Abstract: Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.

Abstract: In an AlGaN channel transistor formed on a <100> orientation silicon wafer, a hole with walls slanted at 54 degrees is etched into the silicon to provide a <111> orientation substrate surface for forming the AlGaN channel transistor.

Abstract: A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.

Abstract: An endoscope includes a light source operable to generate coherent incident light, and a plurality of imaging optical fibres that are arranged in a fibre bundle, arranged to receive light at a proximal end of the fibre bundle, and arranged to transmit light to a distal end of the fibre bundle. The endoscope further includes a spatial light phase modulator between the light source and the fibre bundle, and arranged to receive the incident light from the light source and to adjust the relative phase of the incident light entering each of the plurality of imaging optical fibres.

Abstract: A self-propelled robotic device moves through bodily and other passageways by inflating regions of an overlying bladder along the length of the robotic device in a sequence that imparts motion to the device. The regions of the overlying bladder are inflated by energizing a plurality of coils, which are surrounded by a ferrofluid, in a sequence. The ferrofluid responds to the magnetic field created by an energized coil by creating a bulge in the side wall of the overlying bladder.

Abstract: A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device.