Patents by Inventor William French

William French has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110084607
    Abstract: A method includes forming one or more capacitors over a substrate. The method also includes forming a transformer at least partially over the substrate. The transformer is adjacent to at least one of the one or more capacitors. At least a portion of the transformer is formed at a same level over the substrate as the one or more capacitors. The method further includes coupling the one or more capacitors and the transformer to at least one embedded integrated circuit die. The one or more capacitors, the transformer, and the at least one embedded integrated circuit die form at least part of a light emitting diode (LED) driver.
    Type: Application
    Filed: October 13, 2010
    Publication date: April 14, 2011
    Applicant: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Ann M. Gabrys, William French
  • Patent number: 7913108
    Abstract: Described are a system and method for improving the performance of a disk drive in a data storage system by enabling the disk drive to “ride through” events that can induce disk drive errors. In response to an error message received from a disk drive, a disk director temporarily places the disk drive into a wait state. While in the wait state, the disk drive is prevented from shutting down, despite the current error and any subsequent errors that the disk drive may experience. The disk drive may continue to service I/O requests while in the wait state, with the disk director monitoring the disk drive performance. After the disk drive exits the wait state, the disk director can determine from the monitored results whether to shut down the disk drive or to permit the disk drive to return to normal operation.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: March 22, 2011
    Assignee: EMC Corporation
    Inventors: F. William French, Stephen Richard Ives, Thomas M. De Lucia, Jeffrey R. Berenson, Michael D. Garvey
  • Patent number: 7880261
    Abstract: An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: February 1, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French, Ann Gabrys
  • Patent number: 7849263
    Abstract: A data storage system has a first set of storage devices, a second set of storage devices, and a controller. The controller is arranged to (i) activate a first set of storage devices and deactivate a second set of storage devices prior to an amount of storage capacity currently used in the data storage system reaching a predefined storage capacity threshold of the data storage system. The controller is further arranged to (i) monitor the amount of storage capacity currently used in the data storage system in view of the predefined storage capacity threshold, and (ii) maintain activation of the first set of storage devices and automatically activate the second set of storage devices in response to the amount of storage capacity currently used in the data storage system reaching the predefined storage capacity threshold.
    Type: Grant
    Filed: December 24, 2007
    Date of Patent: December 7, 2010
    Assignee: EMC Corporation
    Inventor: F. William French
  • Publication number: 20100295550
    Abstract: A battery includes multiple conductive plates and a permeable electrolytic material and an ion membrane located between the conductive plates. The battery also includes at least one wire located within one or more of the permeable electrolytic material and the ion membrane. The at least one wire can be configured to regulate a flow of ions through the ion membrane based on an electrical signal flowing through the at least one wire. The at least one wire could also be configured to generate a magnetic field within the permeable electrolytic material based on another electrical signal flowing through the at least one wire. The battery could further include a temperature sensor wire within the permeable electrolytic material.
    Type: Application
    Filed: February 19, 2010
    Publication date: November 25, 2010
    Applicant: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Kyuwoon Hwang, William French, Qingguo Liu
  • Patent number: 7794510
    Abstract: In an on chip battery and method of making an on-chip battery, the electrodes are formed from metal layers deposited as part of the chip fabrication process. An electrolyte is preferably introduced between the electrodes at time of packaging of the chip.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: September 14, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French, Robert Drury, Vladislav Vashchenko
  • Patent number: 7796007
    Abstract: In an on-chip transformer, external electromagnetic field influences are reduced by providing an isolation transformer having primary and secondary windings with a figure 8 configuration so that current induced by an external magnetic field is nulled.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: September 14, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French, Kyuwoon Hwang
  • Publication number: 20100215995
    Abstract: A battery includes multiple conductive battery plates and a complex electrolytic material located between the conductive battery plates. The battery also includes a conductive sensor wire located within the complex electrolytic material. The conductive sensor wire may be configured to generate a magnetic field within the complex electrolytic material based on an electrical signal flowing through the conductive sensor wire. The battery may further include a temperature sensor wire within the complex electrolytic material.
    Type: Application
    Filed: February 10, 2010
    Publication date: August 26, 2010
    Applicant: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Kyuwoon Hwang, Ali Djabbari, William French, Qingguo Liu
  • Patent number: 7754505
    Abstract: A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: July 13, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, William French, Vladislav Vashchenko
  • Patent number: 7751188
    Abstract: A cooling method and system is disclosed which utilizes vortex tubes to generate and direct cold air over heat-generating components of an electronic system.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: July 6, 2010
    Assignee: EMC Corporation
    Inventors: F. William French, Sheldon Joel Gilden, Arthur R. Nigro, Jr.
  • Publication number: 20100140663
    Abstract: In an AlGaN channel transistor formed on a <100> orientation silicon wafer, a hole with walls slanted at 54 degrees is etched into the silicon to provide a <111> orientation substrate surface for forming the AlGaN channel transistor.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 10, 2010
    Inventors: Peter J. Hopper, William French
  • Publication number: 20100144116
    Abstract: In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 10, 2010
    Inventors: Peter J. Hopper, William French, Kyuwoon Hwang
  • Publication number: 20100141374
    Abstract: In an on-chip transformer, external electromagnetic field influences are reduced by providing an isolation transformer having primary and secondary windings with a figure 8 configuration so that current induced by an external magnetic field is nulled.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 10, 2010
    Inventors: Peter J. Hopper, William French, Kyuwoon Hwang
  • Publication number: 20100030607
    Abstract: A digital content management system with methodologies for lifecycle management of digital content is shown and described. In one embodiment, for example, a digital content management system is described that comprises: an ingestion module for receiving from clients various components used to create digital content releases; a polishing module for matching received components to a particular release being created; a packaging module for encoding the received components that were matched for the particular release into a digital package suitable for delivery to one or more digital content providers; and a delivery module for delivering the digital package of the particular release to one or more digital content providers.
    Type: Application
    Filed: March 24, 2009
    Publication date: February 4, 2010
    Applicant: RoyaltyShare, Inc.
    Inventors: Scott A. Holcombe, Kyle Wright, William French, Ryan Daniels, John Knott
  • Publication number: 20100001365
    Abstract: An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000 s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk.
    Type: Application
    Filed: July 1, 2008
    Publication date: January 7, 2010
    Inventors: Peter J. Hopper, William French, Ann Gabrys
  • Publication number: 20090256687
    Abstract: A magnetic guard ring is provided to reduce the susceptibility of a transformer-based data transmission to an externally generated magnetic field. The guard ring structure comprises strategically placed pieces of ferrite material, such as NiFe, that surround the transformer and “steer” the external magnetic field away from the transformer.
    Type: Application
    Filed: August 27, 2008
    Publication date: October 15, 2009
    Inventors: William French, Peter J. Hopper, Kyuwoon Hwang
  • Publication number: 20090239250
    Abstract: The present invention provides an improved method of analysing and obtaining reliable data about the plasma membrane of single cells, using a microfluidic cell analyser. The microfluidic cell analyser of the invention comprises a single cell trap, a manipulator arranged to manipulate the outer surface of a cell in the trap, a detection zone in communication with the single cell trap and a detector.
    Type: Application
    Filed: December 1, 2005
    Publication date: September 24, 2009
    Applicant: Imperial Innovations Limited
    Inventors: David R. Klug, de Mello Andrew, Richard H. Templer, Paul Michael William French, Mark Andrew Aquilla Neil, Oscar Ces, Peter Joseph Jacques Parker, Keith Robert Willison
  • Publication number: 20090218527
    Abstract: A confocal microscope 2 uses as a light source a two-dimensional array of light emitting diodes 4. A two-dimensional array of detector cells 18 in the form of a CCD camera array or a CMOS camera array is provided. A sequence of illumination patterns are generated by the array of light emitting diodes 4. A corresponding sequence of detection patterns are read from the two-dimensional array of detector cells 18. The light emitting diodes may be A1GaInN light emitting diodes generating light in the wavelength 250 nm to 500 nm. The confocal microscope 2 may be fitted to the tip of an endoscope 30.
    Type: Application
    Filed: March 20, 2007
    Publication date: September 3, 2009
    Applicant: IMPERIAL INNOVATIONS LIMITED
    Inventors: Paul Michael William French, Christopher William Dunsby, Mark Andrew Aquilla Neil
  • Publication number: 20090144035
    Abstract: A modified “black box” integrated circuit simulation model is provided that is based only upon on the external steady-state and transient characteristics of a device under test (DUT). The method utilizes probe pulses as well as steady-state I-V and C-V look-up tables. In contrast to conventional black box simulation models, which support only steady-state and small signal frequency analysis, the disclosed method also supports large signal transient analysis.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 4, 2009
    Inventors: Yuri Mirgorodski, Peter J. Hopper, William French, Philipp Lindorfer
  • Patent number: 7531824
    Abstract: An apparatus and method for fabricating high value inductors embedded on semiconductor integrated circuit. The apparatus and method involve forming a conductor on the semiconductor substrate. Once the conductor is formed, a polymer material is provided on the substrate surrounding the conductor. The polymer material contains a ferromagnetic material so that the permeability of the polymer is greater than one. In various embodiments, the ferromagnetic material may be any one of a number of different high permeable materials such as iron oxide, zinc, manganese, zirconium, samarium (SA), neodymium (NA), cobalt, nickel or a combination thereof.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: May 12, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter Johnson, Peter J. Hopper, Kyuwoon Hwang, William French