Patents by Inventor William H. Radke

William H. Radke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL
    Publication number: 20140185620
    Abstract: The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.
    Type: Application
    Filed: December 17, 2013
    Publication date: July 3, 2014
    Applicant: Micron Technology, Inc.
    Inventors: William H. Radke, Victor Y. Tsai, Peter Feeley, Neal A. Galbo, Robert N. Leibowitz
  • MEMORY DEVICES AND SYSTEMS CONFIGURED TO ADJUST A SIZE OF AN ECC COVERAGE AREA
    Publication number: 20140189468
    Abstract: Memory devices and systems having an array of memory cells arranged in a plurality of sectors and a plurality of ECC coverage areas, and control circuitry configured to adjust a size of one or more of the ECC coverage areas.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 3, 2014
    Applicant: Micron Technology, Inc.
    Inventor: William H. RADKE
  • Boot partitions in memory devices and systems
    Patent number: 8762703
    Abstract: The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Neal A. Galbo, Victor Y. Tsai, William H. Radke, Krishnam R. Dalta
  • Data conditioning to improve flash memory reliability
    Patent number: 8762629
    Abstract: Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Vishal Sarin, Jung-Sheng Hoei
  • STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION
    Publication number: 20140164867
    Abstract: The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.
    Type: Application
    Filed: January 22, 2013
    Publication date: June 12, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mustafa N. Kaynak, William H. Radke, Patrick R. Khayat, Sivagnanam Parthasarathy
  • Object oriented memory in solid state devices
    Patent number: 8751860
    Abstract: The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices includes accessing a defined set of data as a single object in an atomic operation manner, where the accessing is from a source other than a host. The embodiment also includes storing the defined set of data as the single object in a number of solid state memory blocks as formatted by a control component of a solid state device that includes the number of solid state memory blocks.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Peter Feeley, Neal A. Galbo, James Cooke, Victor Y. Tsai, Robert N. Leibowitz, William H. Radke
  • NON-SYSTEMATIC CODED ERROR CORRECTION
    Publication number: 20140136926
    Abstract: Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or routines to efficiently detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array, allowing for an increased level of data security. The ECC code is distributed throughout the stored data in the memory segment, increasing the robustness of the ECC code and its resistance to damage or data corruption.
    Type: Application
    Filed: January 16, 2014
    Publication date: May 15, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: William H. Radke, Shuba Swaminathan, Brady L. Keays
  • Fault-tolerant non-volatile integrated circuit memory
    Patent number: 8725937
    Abstract: Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: May 13, 2014
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • Error recovery storage along a memory string
    Patent number: 8713401
    Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • Data modulation for groups of memory cells
    Patent number: 8711617
    Abstract: Methods, devices, and systems for data modulation for groups of memory cells. Data modulation for groups of memory cells can include modulating N units of data to a combination of programmed states. Each memory cell of a group of G number of memory cells can be programmed to one of M number of programmed states, where M is greater than a minimum number of programmed states needed to store N/G units of data in one memory cell, and where the programmed state of each memory cell of the group is one of the combination of programmed states.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Zhenlei Shen, William H. Radke
  • Replacing defective memory blocks in response to external addresses
    Patent number: 8705299
    Abstract: An apparatus has a controller. The controller is configured to address a non-defective memory block of a sequence of memory blocks in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is a proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. The controller is configured to apply a voltage-delay correction to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Dzung H. Nguyen, William H. Radke
  • HOST CONTROLLER
    Publication number: 20140108678
    Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 17, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Peter Feeley, Robert N. Leibowitz, William H. Radke, Neal A. Galbo, Victor. Y. Tsai
  • PROGRAMMING METHODS AND MEMORIES
    Publication number: 20140104958
    Abstract: Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Vishal SARIN, William H. RADKE, Frankie F. ROOHPARVAR
  • METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES
    Publication number: 20140098614
    Abstract: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 10, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Zhenlei Shen, William H. Radke, Peter Feeley
  • Programming methods and memories
    Patent number: 8687431
    Abstract: Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, William H. Radke, Frankie F. Roohparvar
  • POWER CONSUMPTION CONTROL
    Publication number: 20140086000
    Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 27, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Krishnam R. Datla, William H. Radke, Robin Sarno, Laszlo Borbely-Bartis, Ken Kannampuzha
  • Memory cell coupling compensation
    Patent number: 8681547
    Abstract: Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Zhenlei Shen, William H. Radke, Peter Feeley
  • INFERRING THRESHOLD VOLTAGE DISTRIBUTIONS ASSOCIATED WITH MEMORY CELLS VIA INTERPOLATION
    Publication number: 20140063975
    Abstract: The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Zhenlei Shen, William H. Radke
  • STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION
    Publication number: 20140059251
    Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.
    Type: Application
    Filed: September 17, 2013
    Publication date: February 27, 2014
    Applicant: Micron Technology, Inc.
    Inventors: William H. Radke, Victor Y. Tsai, James Cooke, Neal A. Galbo, Peter Feeley
  • Error detection and correction scheme for a memory device
    Patent number: 8661312
    Abstract: Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: February 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Shuba Swaminathan, Brady L. Keays