Patents by Inventor William H. Radke

William H. Radke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY DEVICES FACILITATING DIFFERING DEPTHS OF ERROR DETECTION AND/OR ERROR CORRECTION COVERAGE
    Publication number: 20140047298
    Abstract: Memory devices facilitating differing depths of error detection and/or error correction coverage for differing portions of a memory array.
    Type: Application
    Filed: October 21, 2013
    Publication date: February 13, 2014
    Applicant: Micron Technology, Inc.
    Inventor: William H. Radke
  • BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION
    Publication number: 20140025943
    Abstract: The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.
    Type: Application
    Filed: September 24, 2013
    Publication date: January 23, 2014
    Applicant: Micron Technology, Inc.
    Inventors: William H. Radke, Victor Y. Tsai, Peter Feeley, Neal A. Galbo, Robert N. Leibowitz
  • Non-systematic coded error correction
    Patent number: 8635510
    Abstract: Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. Reduced complexity error detection and correction hardware and/or routines detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array. The ECC code is distributed throughout the stored data in the memory segment.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: January 21, 2014
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Shuba Swaminathan, Brady L. Keays
  • Packet deconstruction/reconstruction and link-control
    Patent number: 8630182
    Abstract: The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Victor Y. Tsai, Peter Feeley, Neal A. Galbo, Robert N. Leibowitz
  • Memory controller ECC
    Patent number: 8627180
    Abstract: Memory controllers having a data buffer coupled to receive and hold data from a memory device, and an Error Correction Code (ECC) generator/checker coupled to the data buffer. The ECC generator/checker is configured to generate ECC codes for the data and to compare the generated ECC codes with ECC codes received with the data. The memory controllers are configured to permit different ECC coverage area sizes and/or different ECC code types for different portions of the memory device.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • FRACTIONAL BITS IN MEMORY CELLS
    Publication number: 20140003143
    Abstract: Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2B, rounded up to an integer, and where B is equal to the fractional number of bits represented by the programmed state.
    Type: Application
    Filed: September 6, 2013
    Publication date: January 2, 2014
    Applicant: Micron Technology, Inc.
    Inventor: William H. Radke
  • CORRECTING DATA IN A MEMORY
    Publication number: 20130332798
    Abstract: Methods of correcting data in a memory, and memories adapted to correct data, include prioritizing error correction of the read data in response to locations and likely states of known bad or questionable data positions of a segment of a memory array selected for reading.
    Type: Application
    Filed: August 12, 2013
    Publication date: December 12, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Brady L. Keays, Shuba Swaminathan, William H. Radke
  • Advanced detection of memory device removal, and methods, devices and connectors
    Patent number: 8599637
    Abstract: Memory devices, connectors and methods for terminating an operation are provided, including a memory device configured to terminate an internal operation such as a programming or erase operation responsive to receiving a signal during removal of the memory device from a connector, such as a socket. The memory device may be configured to generate the removal signal, such as by including a dedicated removal terminal. The memory card may respond to the signal by terminating a programming or erase operation before power is lost. The removal terminal may have a dimension that is different from a dimension of a power terminal. Alternatively, the connector may be configured to generate a signal that causes a host to terminate programming or erase operations prior to memory card removal, such as by including a switch that is actuated when the memory device moves to a pre-power loss position.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: December 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: James Cooke, Peter Feeley, Victor Tsai, William H. Radke, Neal Galbo, Chad Cobbley
  • Methods, devices, and systems for dealing with threshold voltage change in memory devices
    Patent number: 8576632
    Abstract: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: November 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Zhenlei Shen, William H. Radke, Peter Feeley
  • Host controller
    Patent number: 8578070
    Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 5, 2013
    Assignee: Micron Technology
    Inventors: Peter Feeley, Robert N. Leibowitz, William H. Radke, Neal A. Galbo, Victor Y. Tsai
  • DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS
    Publication number: 20130286736
    Abstract: The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.
    Type: Application
    Filed: May 28, 2013
    Publication date: October 31, 2013
    Inventors: William H. Radke, Zhenlei Shen, Peter Feeley
  • ERROR RECOVERY STORAGE ALONG A MEMORY STRING
    Publication number: 20130283130
    Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.
    Type: Application
    Filed: June 17, 2013
    Publication date: October 24, 2013
    Inventor: William H. Radke
  • Data handling
    Patent number: 8566675
    Abstract: Methods and apparatus to facilitate determining or selecting a depth of error detection and/or error correction coverage, and detecting and/or correcting errors in data in accordance with the determined or selected depth of error detection and/or error correction coverage.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: October 22, 2013
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • BOOT PARTITIONS IN MEMORY DEVICES AND SYSTEMS
    Publication number: 20130275713
    Abstract: The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.
    Type: Application
    Filed: April 23, 2013
    Publication date: October 17, 2013
    Inventors: Neal A. Galbo, Victor Y. Tsai, William H. Radke, Krishnam R. Datla
  • REPLACING DEFECTIVE MEMORY BLOCKS IN RESPONSE TO EXTERNAL ADDRESSES
    Publication number: 20130250707
    Abstract: An apparatus has a controller. The controller is configured to address a non-defective memory block of a sequence of memory blocks in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is a proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. The controller is configured to apply a voltage-delay correction to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.
    Type: Application
    Filed: May 15, 2013
    Publication date: September 26, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Sarin Vishal, Dzung H. Nguyen, William H. Radke
  • Booting in systems having devices coupled in a chained configuration
    Patent number: 8543802
    Abstract: The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: September 24, 2013
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Victor Y. Tsai, Peter Feeley, Neal A. Galbo, Robert N. Leibowitz
  • State change in systems having devices coupled in a chained configuration
    Patent number: 8539117
    Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Victor Y. Tsai, James Cooke, Neal A. Galbo, Peter Feeley
  • MEMORY AND SENSE PARAMETER DETERMINATION METHODS
    Publication number: 20130238863
    Abstract: Memory devices and methods for operating a memory include filtering a histogram of sensed data of the memory, and adjusting a parameter used to sense the memory using the filtered histogram. Filtering can be accomplished by averaging or summing, and may include weighting the sums or averages.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Inventors: Zhenlei Shen, William H. Radke
  • Fractional bits in memory cells
    Patent number: 8531877
    Abstract: Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2B, rounded up to an integer, and where B is equal to the fractional number of bits represented by the programmed state.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • Methods of data handling
    Patent number: 8510634
    Abstract: Methods include receiving data and an ECC code read from a memory array, generating an ECC code from the received data, and determining whether the received data is corrupted by evaluating the generated ECC code against the ECC code read from the memory array. If the received data is determined to be corrupted, a correction algorithm and a recorded likely state of a known bad/questionable bit of the received data may be used to correct error in the received data. Alternatively, if the received data is determined to be corrupted, the correction algorithm and a recorded location of a known bad/questionable bit of the received data may be used to correct error in the received data.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: August 13, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Brady L. Keays, Shuba Swaminathan, William H. Radke