Abstract: Systems and methods for managing access to a cache relate to determining one or more execute permissions associated with a write-address of a write-request to the cache. The cache may be a unified cache for storing data as well as instructions. If there is a write-miss in the cache for the write-request, a cache controller may determine whether to implement a write-allocate policy or a write-no-allocate policy for servicing the write-miss, based on the one or more execute permissions. The one or more execute permissions can relate to a privilege level associated with the write-address. Execute permissions of a producing agent which generated the write-request and an execute permission of a consuming agent which can execute from the write-address may be based on the privilege levels of the producing agent and the consuming agent, respectively.

Abstract: Aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in processors. An exemplary method includes detecting a pattern of pipelined instructions to access memory using a first portion of available bus width and, in response to detecting the pattern, combining the pipelined instructions into a single instruction to access the memory using a second portion of the available bus width that is wider than the first portion. Devices including processors using disclosed aspects may execute currently available software in a more efficient manner without the software being modified.

Abstract: Methods and systems are provided for inferring spark plug fouling due to accumulation of fuel additives thereon. In one example, an engine controller may infer spark plug hot fouling based on higher than expected exhaust temperatures by correlating the elevated exhaust temperature with late combustion phasing due to additive accumulation. A confidence factor of the spark plug hot fouling detection may be enhanced based on data regarding concurrent misfire and/or pre-ignition events.

Abstract: A casino electronic gaming machine cabinet is provided, comprising at least one display screen, a plurality of input controls, a dock configured to receive a player's mobile device, and at least one communication interface capable of electronic communication with the player's mobile device via the dock while the mobile device executes wagering game software providing wagering game play to the player. The cabinet further comprises control circuitry configured to transmit to the docked mobile device control signals corresponding to input commands entered by the player via the input controls of the cabinet, and display on the display screen(s) of the cabinet graphics output from the wagering game software received from the player's docked mobile device, providing visual components of the wagering game play.

Abstract: Methods and systems are provided for adjusting an ignition energy provided to an engine cylinder upon reactivation from a VDE mode of operation. Ignition energy is increased by increasing an ignition coil dwell time and/or an ignition coil strike frequency. The increased ignition energy improves combustion stability during the transition out of the VDE mode of operation.

Abstract: Methods and systems are provided for detecting spark plug fouling in an ignition system of an engine. In one example, a method may include directing current flow into a primary winding of an ignition coil of the ignition system for a duration of dwell period responsive to a dwell command from a controller, reducing the current flow to discharge an initial spark, and discharging additional sparks. The method may further include selectively generating an indication of a recommendation to change one or more spark plugs of the ignition system based upon a primary current measured after the dwell period.

Abstract: Predicting memory instruction punts in a computer processor using a punt avoidance table (PAT) are disclosed. In one aspect, an instruction processing circuit accesses a PAT containing entries each comprising an address of a memory instruction. Upon detecting a memory instruction in an instruction stream, the instruction processing circuit determines whether the PAT contains an entry having an address of the memory instruction. If so, the instruction processing circuit prevents the detected memory instruction from taking effect before at least one pending memory instruction older than the detected memory instruction, to preempt a memory instruction punt. In some aspects, the instruction processing circuit may determine, upon execution of a pending memory instruction, whether a hazard associated with the detected memory instruction has occurred. If so, an entry for the detected memory instruction is generated in the PAT.

Abstract: Systems and methods for identifying candidate load instructions for prefetch operations based on at least instruction encoding of the load instructions, include an identifier based on a function of at least one or more fields of a load instruction and optionally, a subset of bits of the PC value of the load instruction, wherein the one or more fields exclude a full address or program counter (PC) value of the load instruction. Prefetch mechanisms, including a prefetch table indexed by the identifier, can determine whether the load instruction is a candidate load instruction for prefetching load data, based on the identifier. The function may be a hash, a concatenation, or a combination thereof, of one or more bits of the one or more fields. The fields include one or more of a base register, a destination register, an immediate offset, an offset register, or other bits of instruction encoding of the load instruction.

Abstract: Methods and systems are provided for addressing spark plug soot fouling. In one example, spark plug tip temperatures are raised and maintained elevated by advancing spark timing and increasing engine speed, while reducing an amount of EGR being delivered to the engine. The spark plug fouling mitigating actions are adjusted based on whether the engine is in a green condition at an assembly plant or not.

Abstract: Methods and systems are provided for addressing spark plug soot fouling. In one example, a method may include alternating one or more combustion events with spark timing advanced with one or more combustion events with nominal spark timing. The approach allows spark plug over-heating, and related issues such as knock, to be reduced.

Abstract: Methods and systems are provided for inferring spark plug fouling due to accumulation of fuel additives thereon. In one example, an engine controller may infer spark plug hot fouling based on higher than expected exhaust temperatures by correlating the elevated exhaust temperature with late combustion phasing due to additive accumulation. A confidence factor of the spark plug hot fouling detection may be enhanced based on data regarding concurrent misfire and/or pre-ignition events.

Abstract: Methods and systems are provided for inferring spark plug fouling due to accumulation of fuel additives thereon. In one example, an engine controller may infer spark plug fouling due to accumulation of fuel additive based on a combination of engine operating parameters correlated with spark plug health. For example, the engine operating parameters may include a change in an adaptive knock term, an engine pre-ignition rate, and engine exhaust oxygen sensor switching frequency over a vehicle drive cycle, and an engine misfire rate.

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract: Systems and methods for mitigating influence of wrong-path branch instructions in branch prediction include a branch prediction write queue. A first entry of the branch prediction write queue is associated with a first branch instruction based on an order in which the first branch instruction is fetched. Upon speculatively executing the first branch instruction, a correct direction of the first branch instruction is written in the first entry. Prior to committing the first branch instruction, the branch prediction write queue is configured to update one or more branch prediction mechanisms based on the first entry if the first branch instruction was speculatively executed in a correct-path. Updates to the one or more branch prediction mechanisms based on the first entry are prevented if the first branch instruction was speculatively executed in a wrong-path.

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract: Indexing subroutine entries in a branch target instruction cache (BTIC) using a target address of the subroutine. The instructions returned by the BTIC may be injected into an execution pipeline to remove a cycle bubble in the processing pipeline.

Abstract: Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction indicating an operation writing an immediate value to a register is detected by an instruction processing circuit. The circuit also detects at least one subsequent instruction indicating an operation that overwrites at least one first portion of the register while maintaining a value of a second portion of the register. The at least one subsequent instruction is converted (or replaced) with a fused instruction(s), which indicates an operation writing the at least one first portion and the second portion of the register.

Abstract: The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor.

Abstract: Removing invalid literal load values, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit provides a literal load table containing one or more entries comprising an address and a cached literal load value. Upon detecting a literal load instruction in an instruction stream, the instruction processing circuit determines whether the literal load table contains an entry having an address of the literal load instruction. If so, the instruction processing circuit removes the literal load instruction from the instruction stream, and provides the cached literal load value stored in the entry to at least one dependent instruction. The instruction processing circuit further determines whether an invalidity indicator for the literal load table has been received. If so, the instruction processing circuit flushes the literal load table. The invalidity indicator may be generated responsive to modification of a constant table.

Abstract: According to some aspects, a method of operating a casino game is provided comprising obtaining indications of communication latency from the server to at least a first gaming device and a second gaming device, receiving first user input data from the first gaming device, the first user input data being indicative of a wager, determining an outcome for the first instance of the casino game based at least in part on the wager, and, based at least in part on the indications of communication latency from the server to the first and second gaming devices, sending first image data to the first gaming device through wired communication channels, the first image data including one or more visual indications of the outcome, and sending second image data to the second gaming device through at least one wireless communication channel.