Abstract: A processor to a store constant value (immediate or literal) in a cache upon decoding a move immediate instruction in which the immediate is to be moved (copied or written) to an architected register. The constant value is stored in an entry in the cache. Each entry in the cache includes a field to indicate whether its stored constant value is valid, and a field to associate the entry with an architected register. Once a constant value is stored in the cache, it is immediately available for forwarding to a processor pipeline where a decoded instruction may need the constant value as an operand.

Abstract: Methods and apparatuses for optimizing hard-to-predict short forward branches. A method detects a forward conditional branch with at least one instruction between the forward conditional branch and forward conditional branch target. The method determines whether a first of the at least one instruction includes at least one of a conditional branch or a condition-code setter. If the first instruction does not have the at least one of a conditional branch or a condition-code setter, the first instruction is dynamically assigned an inverted condition to optimize a code path. The method determines if there is a next instruction between the forward conditional branch and its target. If there is, the method analyzes the next instruction. If there is no next instruction, the method executes the optimized code path. If the instruction includes the conditional branch or condition-code setter, it discards dynamic assignments and executes the detected forward conditional branch.

Abstract: A kit (400) for use in performing joint arthroplasty is provided. The kit (400) includes a trial (12) and a reamer (2). The reamer (2) is for preparing a cavity (4) in the intramedullary canal (8) of a long bone (8) with the use of a driver (10) and to assist in performing a trial reduction. The reamer (2) includes a first portion (14) for placement at least partially in the cavity (4) of the long bone (8) and a second portion (16) operably connected to the first portion (14). The reamer (2) is removably connected to the driver (10) to rotate the reamer (2). The trial (12) is removably attachable to the reamer (2).

Abstract: Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.

Abstract: Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction indicating an operation writing an immediate value to a register is detected by an instruction processing circuit. The circuit also detects at least one subsequent instruction indicating an operation that overwrites at least one first portion of the register while maintaining a value of a second portion of the register. The at least one subsequent instruction is converted (or replaced) with a fused instruction(s), which indicates an operation writing the at least one first portion and the second portion of the register.

Abstract: Methods and systems are provided for purging condensate from a charge air cooler to an engine intake while reducing misfire events related to the water ingestion. During the purging, a spark timing is adjusted based on the amount of condensate purged per cycle. The spark timing is adjusted differently when the condensate is purged during a tip-in versus a pro-active clean-out routine.

Abstract: Fusing flag-producing and flag-consuming instructions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a flag-producing instruction indicating a first operation generating a first flag result is detected in an instruction stream by an instruction processing circuit. The instruction processing circuit also detects a flag-consuming instruction in the instruction stream indicating a second operation consuming the first flag result as an input. The instruction processing circuit generates a fused instruction indicating the first operation generating the first flag result and indicating the second operation consuming the first flag result as the input. In this manner, as a non-limiting example, the fused instruction eliminates a potential for a read-after-write hazard between the flag-producing instruction and the flag-consuming instruction.

Abstract: A processor architecture to qualify software target-branch hints with hardware-based predictions, the processor including a branch target address cache having entries, where an entry includes a tag field to store an instruction address, a target field to store a target address, and a state field to store a state value. Upon decoding an indirect branch instruction, the processor determines whether an entry in the branch target address cache has an instruction address that matches the address of the decoded indirect branch instruction; and if there is a match, depending upon the state value stored in the entry, the processor will use the stored target address as the predicted target address for the decoded indirect branch instruction, or will use a software provided target address hint if available.

Abstract: Compositions, devices, and methods are contemplated for predicting a patient's likelihood of having a disease. An antigen composition can have a plurality of autoantibody reactive antigens associated with a carrier, where at least two of the antigens have quantified and known relative autoantibody reactivities with respect to sera of a population affected by a disease. The at least two antigens can also have a known association with a disease parameter. A method can include determining autoantibody reactivity against one or more antigens or their variants in a serum sample obtained from a patient, where the autoantibody reactivity against one or more of the antigens indicates an increased likelihood of the patient having a disease.

Abstract: The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor.

Abstract: Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.

Abstract: Eliminating redundant masking operations in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction in an instruction stream indicating an operation writing a value to a first register is detected by an instruction processing circuit, the value having a value size less than a size of the first register. The circuit also detects a second instruction in the instruction stream indicating a masking operation on the first register. The masking operation is eliminated upon a determination that the masking operation indicates a read operation and a write operation on the first register and has an identity mask size equal to or greater than the value size. in this manner, the elimination of the masking operation avoids potential read-after-write hazards and improves performance of a CPU by removing redundant operations from an execution pipeline.

Abstract: A method for retrieving a return address from a link stack when returning from a procedure in a pipeline processor is disclosed. The method identifies a retrieve instruction operable to retrieve a return address from a software stack. The method further identifies a branch instruction operable to branch to the return address. The method retrieves the return address from the link stack, in response to both the instruction and the branch instruction being identified and fetches instructions using the return address.

Abstract: Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.

Abstract: A processor implements an apparatus and a method for predicting an indirect branch address. A target address generated by an instruction is automatically identified. A predicted next program address is prepared based on the target address before an indirect branch instruction utilizing the target address is speculatively executed. The apparatus suitably employs a register for holding an instruction memory address that is specified by a program as a predicted indirect address of an indirect branch instruction. The apparatus also employs a next program address selector that selects the predicted indirect address from the register as the next program address for use in speculatively executing the indirect branch instruction.

Abstract: A gaming machine arranged to implement a base game and associated method are described. The gaming machine includes a game implementer arranged to implement a game and to generate game state information indicative of the current state of the game as the game is played by a player; and a data storage device arranged to store the game state information as the game is played by the player; the game implementer being arranged to retrieve game state information and to recommence play of the game by the player when the game state information is retrieved.

Abstract: When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X % into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.

Abstract: A gaming system comprising a gaming machine, a switching mechanism connected between a game controller and an audio visual output device, and an external controller in data communication with the game controller via a first communications link and connected via a second communications link to the switching mechanism. The gaming system is arranged such that, in a first mode, the game controller generates first game events based on the player input and outputs first audio visual data related to the first game events, and the gaming system controls the switching mechanism such that the first audio visual data is routed to the audio visual output device, and, in a second mode, the external controller generates second game events and outputs second audio visual data related to the second game events on the second communications link, and the gaming system controls the switching mechanism such that the second audio visual data is routed to the audio visual output device.

Abstract: Circuits and related systems and methods for providing virtual address translation are disclosed. In one embodiment, a circuit comprises a comparator configured to receive as an input a current virtual address and a current attribute associated with the current virtual address, and a prior physical address and a prior virtual address each associated with the current attribute. The comparator is further configured to cause the prior physical address to be provided as a current physical address if the current virtual address matches the prior virtual address associated with the current attribute. As an example, the circuit may be a TLB suppression circuit configured to reduce TLB lookups. Reducing TLB lookups can reduce power dissipation. In this regard, the circuit may also be further configured to suppress a TLB lookup to reduce power dissipation when the current virtual address matches the prior virtual address.

Abstract: According to the methods and apparatus taught herein, processor caching policies are determined using cache policy information associated with a target memory device accessed during a memory operation. According to one embodiment of a processor, the processor comprises at least one cache and a memory management unit. The at least one cache is configured to store information local to the processor. The memory management unit is configured to set one or more cache policies for the at least one cache. The memory management unit sets the one or more cache policies based on cache policy information associated with one or more target memory devices configured to store information used by the processor.