Abstract: A method for determining degraded valve operation. According to the method, valve degradation can be determined from the duration of a spark event. This method allows for the determination of both intake and exhaust valve degradation.

Abstract: A system and method taught herein control data prefetching for a data cache by tracking prefetch hits and overall hits for the data cache. Data prefetching for the data cache is disabled based on the tracking of prefetch hits and data prefetching is enabled for the data cache based on the tracking of overall hits. For example, in one or more embodiments, a cache controller is configured to track a prefetch hit rate reflecting the percentage of hits on the data cache that involve prefetched data lines and disable data prefetching if the prefetch hit rate falls below a defined threshold. The cache controller also tracks an overall hit rate reflecting the overall percentage of data cache hits (versus misses) and enables data prefetching if the overall hit rate falls below a defined threshold.

Abstract: A method for determining degraded valve operation. According to the method, valve degradation can be determined from the duration of a spark event. This method allows for the determination of both intake and exhaust valve degradation.

Abstract: A method for determining degraded valve operation. According to the method, valve degradation can be determined from the duration of a spark event. This method allows for the determination of both intake and exhaust valve degradation.

Abstract: Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.

Abstract: A technique for reducing lookups to a branch target address cache (BTAC) is disclosed. In this technique, a branch target address is retrieved from the BTAC in response to a miss in looking up an instruction address in an instruction cache (I-cache). The branch target address is associated with the instruction address. The branch target address retrieved from the BTAC is stored in the I-cache. With this disclosed technique, subsequent instruction addresses are looked up in the I-cache, nonparallel to the BTAC, thus saving power by reducing needless BTAC lookups.

Abstract: In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for fetching an instruction in the data cache after having a miss in an instruction cache to improve the processor's performance. If an instruction is not present in the instruction cache, an instruction fetch address is sent as a data fetch address to the data cache. If there is valid data present in the data cache at the supplied instruction fetch address, the data actually is an instruction and the data cache entry is fetched and supplied as an instruction to the processor complex. An additional bit may be included in an instruction page table to indicate on a miss in the instruction cache that the data cache should be checked for the instruction.

Abstract: A method for retrieving a return address from a link stack when returning from a procedure in a pipeline processor is disclosed. The method identifies a retrieve instruction operable to retrieve a return address from a software stack. The method further identifies a branch instruction operable to branch to the return address. The method retrieves the return address from the link stack, in response to both the instruction and the branch instruction being identified and fetches instructions using the return address.

Abstract: A method for determining degraded valve operation. According to the method, valve degradation can be determined from the duration of a spark event. This method allows for the determination of both intake and exhaust valve degradation.

Abstract: Certain embodiments provide an electronic gaming component including an audio visual (A/V) device having an A/V output; an A/V input arranged to obtain a signal indicative of an A/V output of at least one peer electronic gaming component; and a controller in communication with the A/V input and arranged to control the A/V output of the A/V device based on the obtained signal. Certain embodiments provide a method of controlling an audio visual (A/V) device of an electronic gaming component including obtaining a signal indicative of the A/V output of at least one peer gaming machine; and controlling the output of the A/V device of the electronic gaming component based on the obtained signal.

Abstract: A system and method taught herein control data prefetching for a data cache by tracking prefetch hits and overall hits for the data cache. Data prefetching for the data cache is disabled based on the tracking of prefetch hits and data prefetching is enabled for the data cache based on the tracking of overall hits. For example, in one or more embodiments, a cache controller is configured to track a prefetch hit rate reflecting the percentage of hits on the data cache that involve prefetched data lines and disable data prefetching if the prefetch hit rate falls below a defined threshold. The cache controller also tracks an overall hit rate reflecting the overall percentage of data cache hits (versus misses) and enables data prefetching if the overall hit rate falls below a defined threshold.

Abstract: An apparatus for recognizing a subroutine call is disclosed. The apparatus includes a circuit comprising a first input for receiving contents of a register, a second input for receiving a non-sequential change in program flow, and a third input for receiving the next sequential address after the non-sequential change in program flow. The circuit is configured to compare the next sequential address and the contents of the register to determine whether the non-sequential change in program flow is a subroutine call.

Abstract: According to the methods and apparatus taught herein, processor caching policies are determined using cache policy information associated with a target memory device accessed during a memory operation. According to one embodiment of a processor, the processor comprises at least one cache and a memory management unit. The at least one cache is configured to store information local to the processor. The memory management unit is configured to set one or more cache policies for the at least one cache. The memory management unit sets the one or more cache policies based on cache policy information associated with one or more target memory devices configured to store information used by the processor.

Abstract: When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X % into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.

Abstract: An apparatus for recognizing a subroutine call is disclosed. The apparatus includes a circuit comprising a first input for receiving contents of a register, a second input for receiving a non-sequential change in program flow, and a third input for receiving the next sequential address after the non-sequential change in program flow. The circuit is configured to compare the next sequential address and the contents of the register to determine whether the non-sequential change in program flow is a subroutine call.

Abstract: An instruction cache controller uses supplemental memory to store a redundant copy of cached instruction data corresponding to a cache boundary position, and thereby enables subsequent single cache access retrieval of an instruction that crosses that boundary position. In one or more embodiments, the cache controller duplicates instruction data for the post-boundary position in the supplemental memory, and multiplexes that copied data into cache data obtained from the pre-boundary position.

Abstract: A technique for reducing lookups to a branch target address cache (BTAC) is disclosed. In this technique, a branch target address is retrieved from the BTAC in response to a miss in looking up an instruction address in an instruction cache (I-cache). The branch target address is associated with the instruction address. The branch target address retrieved from the BTAC is stored in the I-cache. With this disclosed technique, subsequent instruction addresses are looked up in the I-cache, nonparallel to the BTAC, thus saving power by reducing needless BTAC lookups.

Abstract: An air purifier has an air flow cavity bounded by cavity walls and a source of ultraviolet light emitting ultraviolet light within the cavity. The cavity walls have an ultraviolet light reflective coating. A plurality of photocatalytic particles are associated with the reflective coating. The photocatalytic particles are of a type which leads to production of oxygen and hydroxyl free radicals when illuminated with ultraviolet light in the presence of water.

Abstract: A pitching screen which provides a first pitching lane and a second pitching lane in a single pitching screen configuration to allow both left-handed pitchers and right-handed pitchers to pitch without repositioning the pitching screen.

Abstract: An asexually reproduced new variety of Cynodon dactylon with a unique combination of morphological characters including superior turf performance characterized by dense prostrate habit, slow rate of lateral spread, short internode length, low numbers of inflorescences and inflorescence spikes, and a dark green colour.