Abstract: A method for synchronizing a casino game playable at a plurality of gaming devices is provided. The method includes receiving, by a server having at least one processor, an indication of a wager from at least one of the plurality of gaming devices, determining, by the server, a schedule for at least one jackpot of the casino game based at least in part on the received indication of the wager, and sending, by the server, the schedule for the at least one jackpot of the casino game to at least a first gaming device and a second gaming device, the sending including sending the schedule to the first gaming device through wired communication channels, and sending the schedule to the second gaming device through at least one wireless communication channel.

Abstract: A method for synchronizing a casino game playable at a plurality of gaming devices is provided. The method includes receiving, by a server having at least one processor, an indication of a wager from at least one of the plurality of gaming devices, obtaining, by the server, indications of communication latency from the server to at least a first gaming device and a second gaming device of the plurality of gaming devices, and sending, by the server, game outcome determinations to at least the first and second gaming devices, the sending including sending a first game outcome determination to the first gaming device through wired communication channels, and sending a second game outcome determination to the second gaming device through at least one wireless communication channel, wherein sending the first and second game outcome determinations is based at least in part on the indications of communication latency.

Abstract: Methods and systems are provided for detecting spark plug fouling in an ignition system of an engine. In one example, a method may include directing current flow into a primary winding of an ignition coil of the ignition system for a duration of dwell period responsive to a dwell command from a controller, reducing the current flow to discharge an initial spark, and discharging additional sparks. The method may further include selectively generating an indication of a recommendation to change one or more spark plugs of the ignition system based upon a primary current measured after the dwell period.

Abstract: Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.

Abstract: Accelerating constant value generation using a computed constants table, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit provides a computed constants table containing one or more entries each comprising an address and a constant value. The instruction processing circuit is configured to detect, in an instruction stream, a constant-generating instruction sequence, and to determine whether an address of the constant-generating instruction sequence is present in an entry of the computed constants table. If the address of the constant-generating instruction sequence is present in the entry of the computed constants table, the instruction processing circuit provides a constant value stored in the entry for execution of at least one dependent instruction on the constant-generating instruction sequence.

Abstract: Propagating constant values using a computed constants table, and related apparatuses and methods are disclosed. In one aspect, an apparatus comprises an instruction processing circuit configured to provide a computed constants table containing one or more entries. Each entry of the computed constants table comprises an attribute and a computed constant value. The instruction processing circuit is configured to detect a deterministic instruction in an instruction stream. Upon detecting the deterministic instruction, the instruction processing circuit determines whether an attribute of the deterministic instruction matches an entry of the computed constants table. If so, the instruction processing circuit provides the computed constant value stored in the entry to at least one dependent instruction. In this manner, a computed constant value may be propagated between instructions without requiring the deterministic instruction to be re-executed.

Abstract: Predicting literal load values using a literal load prediction table, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit provides a literal load prediction table containing one or more entries, each comprising an address and a literal load value. Upon detecting a literal load instruction in an instruction stream, the instruction processing circuit determines whether the literal load prediction table contains an entry having an address of the literal load instruction. If so, the instruction processing circuit provides the predicted literal load value stored in the entry to at least one dependent instruction. The instruction processing circuit subsequently determines whether the predicted literal load value matches the actual literal load value loaded by the literal load instruction. If a mismatch exists, the instruction processing circuit initiates a misprediction recovery.

Abstract: Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.

Abstract: Methods and systems are provided for purging condensate from a charge air cooler to an engine intake while reducing misfire events related to the water ingestion. During the purging, a spark timing is adjusted based on the amount of condensate purged per cycle. The spark timing is adjusted differently when the condensate is purged during a tip-in versus a pro-active clean-out routine.

Abstract: Eliminating redundant masking operations in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction in an instruction stream indicating an operation writing a value to a first register is detected by an instruction processing circuit, the value having a value size less than a size of the first register. The circuit also detects a second instruction in the instruction stream indicating a masking operation on the first register. The masking operation is eliminated upon a determination that the masking operation indicates a read operation and a write operation on the first register and has an identity mask size equal to or greater than the value size. In this manner, the elimination of the masking operation avoids potential read-after-write hazards and improves performance of a CPU by removing redundant operations from an execution pipeline.

Abstract: Described is a method for cross-referencing one or more defined entities against a system configuration, system component configuration and/or system IT asset configuration to thereby validate applicability, non-applicability, compliance and/or non-compliance of a policy, set of policies, and/or policy checks with respect to the system, system component and/or system IT asset configuration. Also described are an apparatus and a machine-readable medium for performing this method.

Abstract: Described is a method for cross-referencing one or more defined entities against a system configuration, system component configuration and/or system IT asset configuration to thereby validate applicability, non-applicability, compliance and/or non-compliance of a policy, set of policies, and/or policy checks with respect to the system, system component and/or system IT asset configuration. Also described are an apparatus and a machine-readable medium for performing this method.

Abstract: Described is a method for cross-referencing one or more defined entities against a system configuration, system component configuration and/or system IT asset configuration to thereby validate applicability, non-applicability, compliance and/or non-compliance of a policy, set of policies, and/or policy checks with respect to the system, system component and/or system IT asset configuration. Also described are an apparatus and a machine-readable medium for performing this method.

Abstract: Described is a method for cross-referencing one or more defined entities against a system configuration, system component configuration and/or system IT asset configuration to thereby validate applicability, non-applicability, compliance and/or non-compliance of a policy, set of policies, and/or policy checks with respect to the system, system component and/or system IT asset configuration. Also described are an apparatus and a machine-readable medium for performing this method.

Abstract: Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.

Abstract: Methods and systems are provided for inferring spark plug fouling due to accumulation of fuel additives thereon. In one example, an engine controller may infer spark plug fouling due to accumulation of fuel additive based on a combination of engine operating parameters correlated with spark plug health. For example, the engine operating parameters may include a change in an adaptive knock term, an engine pre-ignition rate, and engine exhaust oxygen sensor switching frequency over a vehicle drive cycle, and an engine misfire rate.

Abstract: Methods and systems are provided for determining a type of spark plug fouling. In one example, a method may include differentiating spark plug fouling due to soot accumulation from spark plug fouling due to fuel additive accumulation based on a current on a control wire of the spark plug following application of a dwell command. Further, exhaust oxygen sensor degradation and/or exhaust catalyst degradation may be determined based on switching frequencies of one or more exhaust oxygen sensors and the type of spark plug fouling.

Abstract: Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.

Abstract: Methods and systems are provided for adjusting an ignition energy provided to an engine cylinder upon reactivation from a VDE mode of operation. Ignition energy is increased by increasing an ignition coil dwell time and/or an ignition coil strike frequency. The increased ignition energy improves combustion stability during the transition out of the VDE mode of operation.

Abstract: A kit for use in performing joint arthroplasty is provided. The kit (400) includes a trial (12) and a reamer (2). The reamer (2) is for preparing a cavity (4) in the intramedullary canal (8) of a long bone (8) with the use of a driver (10) and to assist in performing a trial reduction. The reamer (2) includes a first portion (14) for placement at least partially in the cavity (4) of the long bone (8) and a second portion (16) operably connected to the first portion (14). The reamer (2) is removably connected to the driver (10) to rotate the reamer (2). The trial (12) is removably attachable to the reamer (2).