Abstract: A carrier generator includes a phase accumulator configured to generate a phase reference signal based on a frequency command word (FCW) signal, a time to digital converter (TDC) configured to generate a feedback signal based on a divided signal, a loop filter configured to generate a filtered command signal based on the phase reference signal and the feedback signal, and a plurality of tuning arrangements. Each tuning arrangement includes an oscillator configured to receive the filtered command signal and output an adjustment signal, and is configured to output a carrier signal of a corresponding plurality of carrier signals based on the adjustment signal. The divided signal is based on the adjustment signal of a first tuning arrangement.

Abstract: A communication system includes a carrier generator, a first modulation circuit, a pulse generator, a first transmission line, and a second transmission line. The carrier generator is configured to generate a first carrier signal and a reference clock signal. The first modulation circuit is coupled to the carrier generator, and configured to generate a first modulated signal based on a first data signal and the first carrier signal. The pulse generator is coupled to the carrier generator, and configured to generate a pulse train signal based on the reference clock signal. The first transmission line is configured to carry the modulated signal, and configured to cause a delay to the first modulated signal. The second transmission line is coupled to the pulse generator, configured to carry the pulse train signal, and configured to cause a delay to the pulse train signal.

Abstract: A radio frequency interconnect (RFI) includes a transmitter side connected to a first end of a channel, a receiver side connected to a second end of the channel opposite the first end and a calibration system. The receiver side includes at least one of the following configurations: (a) at least one gain control amplifier (GCA) or at least one analog to digital converter (ADC). The calibration system is configured to transmit a predetermined data set through the channel, receive an output from the at least one ADC or the at least one GCA, and calibrate the at least one ADC or the at least one GCA based on a measured data set. The output includes the measured data set based on the predetermined data set transmitted through channel.

Abstract: A communication system includes a carrier generator configured to generate a first carrier signal and a demodulator configured to demodulate a modulated signal responsive to the first carrier signal. The demodulator includes a filter and a gain adjusting circuit. The filter is configured to filter a first signal. The first signal is a product of the first carrier signal and the modulated signal. The filter has a first cutoff frequency and a gain. The gain of the filter is controlled by a set of control signals. The gain adjusting circuit is configured to adjust the gain of the filter based on a voltage of the filtered first signal or a voltage of a second signal. The adjustable gain circuit is configured to generate the set of control signals.

Abstract: A radio frequency interconnect includes a transmitter coupled with an input end of a transmission line, and a receiver coupled with an output end of the transmission line. The transmitter includes a first carrier generator configured to generate a clock recovery signal based on a carrier signal, to output a reference clock signal, and to transmit the clock recovery signal to the receiver. The transmitter also includes a modulator configured to modulate a data packet based on the carrier signal. The transmitter also includes a preamble generator configured to generate and add a preamble to data to generate the data packet. The preamble includes a data sequence associated with the reference clock signal. The transmitter further includes a transmitter output configured to transmit the modulated data packet to the receiver by the transmission line.

Abstract: A circuit includes a transmitter associated with a carrier of a radio frequency interconnect, a transmission channel communicatively coupled with the transmitter, and a receiver communicatively coupled with the transmission channel, the receiver also being associated with the carrier of the radio frequency interconnect. A combiner on a transmitter-side of the transmission channel is coupled between the transmitter and the transmission channel, and a decoupler on a receiver-side of the transmission channel is coupled between the receiver and the transmission channel. A channel loss compensation circuit is communicatively coupled between the transmitter and the receiver.

Abstract: A demodulator is configured to demodulate a modulated signal responsive to a first carrier signal. The demodulator includes a filter and a bandwidth adjusting circuit. The filter is configured to filter a first signal. The first signal is a product of the first carrier signal and the modulated signal. The filter has a bandwidth adjusted based on a set of control signals. The bandwidth adjusting circuit is coupled to the filter, and configured to generate the set of control signals based on at least a frequency of the filtered first signal and a frequency of the first signal. The bandwidth adjusting circuit includes a frequency detector configured to generate a second signal based on a frequency relationship between the frequency of the filtered first signal and the frequency of the first signal.

Abstract: A device, a circuit and a method are disclosed herein. The device includes a data receiving circuit and an oscillating signal generator. The data receiving circuit is configured to output a first output signal, a second output signal, and a phase error signal according to an oscillating signal and a modulated signal, in which the phase error signal indicates a phase difference between the oscillating signal and the modulated signal. The oscillating signal generator is configured to delay a phase of a first reference signal according to the phase error signal, to generate the oscillating signal.

Abstract: A digital code recovery circuit includes a data transmitter that outputs either input data or a preamble code as transmitter data. A radio frequency interconnect (RFI) transmitter modulates carrier signals based on the transmitter data and transmits the modulated carrier signals over a channel to an RFI receiver that demodulates the carrier signals to obtain recovered transmitter data. A calibration storage device stores preamble data and a calibration circuit receives the recovered transmitter data. If the recovered transmitter data originated from the preamble code, the calibration circuit determines a set of digital calibration adjustments from the recovered transmitter data and the preamble data. If the recovered transmitter data originated from the input data, the calibration circuit applies the set of digital calibration adjustments to the recovered transmitter data to obtain adjusted digital code and outputs the adjusted digital code.

Abstract: An integrated circuit includes a first radio frequency interconnect (RFI) transceiver, a second RFI transceiver, a third RFI transceiver, a fourth RFI transceiver and a guided transmission medium. The first RFI transceiver is configured to transmit or receive a first data signal. The second RFI transceiver is configured to transmit or receive a second data signal. The third RFI transceiver is configured to transmit or receive the first data signal. The fourth RFI transceiver is configured to transmit or receive the second data signal. The guided transmission medium is configured to carry the first data signal and the second data signal. The first RFI transceiver and the second RFI transceiver are connected to the third RFI transceiver and the fourth RFI transceiver by the guided transmission medium.

Abstract: A transceiver group includes a plurality of transceivers; wherein the transceiver group performs transmission and receiving through a wire, and each of the transceivers includes a transmitter and a receiver, and the transmitter includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for a plurality of data streams to be transmitted; a modulator, coupled to the data streams to be transmitted and the carrier generator, to generate a plurality of modulated data streams carried on the plurality of carriers; and a summer arranged to merge the plurality of modulated data streams to an output signal to the wire; and the receiver includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for an input signal received from the wire; and a demodulator, coupled to the input signal and the carrier generator, to generate a plurality of demodulated data streams.

Abstract: A carrier generator includes a phase accumulator configured to receive a frequency command word (FCW) signal. The carrier generator includes an adder connected to the phase accumulator; and a loop filter configured to receive an output of the adder. The carrier generator includes a plurality of tuning arrangements, each tuning arrangement is configured to receive an output of the loop filter. Each tuning arrangement includes an electronic oscillator configured to receive the output of the loop filter. Each tuning arrangement includes a voltage controlled delay line (VCDL) configured to receive an output of the electronic oscillator, and to provide a tuning arrangement output. Each tuning arrangement includes a phase detector configured to receive a corresponding recovered clock signal and a feedback from a corresponding tuning arrangement output. Each tuning arrangement includes a counter configured to receive an output of the phase detector and to provide an output to the VCDL.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Abstract: A communication system includes a transmitter, a first transmission line, and a second transmission line. The transmitter includes a modulation circuit, a carrier generator, and a pulse generator. The modulation circuit is configured to modulate a first data stream based on a first carrier signal, thereby generating a modulated signal. The carrier generator is configured to generate the first carrier signal and a reference clock signal. The pulse generator is configured to generate a pulse train signal based on the reference clock signal. The first transmission line is configured to carry the modulated signal. The second transmission line is configured to carry the pulse train signal.

Abstract: A communication system includes a carrier generator configured to generate a first carrier signal and a demodulator configured to demodulate a modulated signal responsive to the first carrier signal. The demodulator includes a filter and a bandwidth adjusting circuit. The filter is configured to filter a first signal. The first signal is a product of the first carrier signal and the modulated signal. The filter has a first cutoff frequency and a bandwidth. The bandwidth of the filter is controlled by a set of control signals. The bandwidth adjusting circuit is configured to adjust the bandwidth of the filter based on a frequency of the filtered first signal and a frequency of the first signal, or a phase of the filtered first signal and a phase of the first signal. The bandwidth adjusting circuit is configured to generate the set of control signals.

Abstract: A radio frequency interconnect includes a plurality of transmitters. Each transmitter is associated with an individual carrier of a plurality of carriers. The radio frequency interconnect also includes a transmission channel communicatively coupled with the transmitters and a plurality of receivers communicatively coupled with the transmission channel. Each receiver is associated with a respective carrier. A combiner on a transmitter-side of the transmission channel is coupled with the transmitters between the transmitters and the transmission channel. A decoupler on a receiver-side of the transmission channel is coupled with the receivers between the receivers and the transmission channel. The radio frequency interconnect also includes at least one channel loss compensation circuit communicatively coupled between the plurality of transmitters and the plurality of receivers.

Abstract: A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.

Abstract: A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.