Patents by Inventor William Wu Shen
William Wu Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140282305Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
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Publication number: 20140239427Abstract: Some embodiments relate to a semiconductor module comprising a low-cost integrated antenna that uses a conductive backside structure in conjunction with a ground metal layer to form a large ground plane with a small silicon area. In some embodiments, the integrated antenna structure has an excitable element that radiates electromagnetic radiation. An on-chip ground plane, located on a first side of an interposer substrate, is positioned below the excitable element. A compensation ground plane, located on an opposing side of the interposer substrate, is connected to the ground plane by one or more through-silicon vias (TSVs) that extend through the interposer substrate. The on-chip ground plane and the compensation ground collectively act to reflect the electromagnetic radiation generated by the excitable element, so that the compensation ground improves the performance of the on-chip ground plane.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
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Publication number: 20140126274Abstract: A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals.Type: ApplicationFiled: November 2, 2012Publication date: May 8, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsien-Hsin Sean LEE, William Wu SHEN, Yun-Han LEE
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Patent number: 8701073Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of a plurality of points of the 3D-IC design, and outputting data representing the potential thermal violation. The 3D-IC model represents a 3D-IC design comprising a plurality of elements in a stack configuration. The power profile is applied to the plurality of elements of the 3D-IC design as a function of an operating time. The transient temperature profile includes temperatures at a plurality of points of the 3D-IC design as a function of an operating time.Type: GrantFiled: November 21, 2012Date of Patent: April 15, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-min Fu, William Wu Shen, Po-Hsiang Huang, Meng-Fu You, Chi-Yeh Yu
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Publication number: 20140096102Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of a plurality of points of the 3D-IC design, and outputting data representing the potential thermal violation. The 3D-IC model represents a 3D-IC design comprising a plurality of elements in a stack configuration. The power profile is applied to the plurality of elements of the 3D-IC design as a function of an operating time. The transient temperature profile includes temperatures at a plurality of points of the 3D-IC design as a function of an operating time.Type: ApplicationFiled: November 21, 2012Publication date: April 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-min FU, William Wu SHEN, Po-Hsiang HUANG, Meng-Fu YOU, Chi-Yeh YU
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Patent number: 7061821Abstract: The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array. Techniques are advanced involving data responsive selectable array circuitry modification for such operations as address correctness verification, machine timing and component drift correction purposes. The principles are illustrated with memory systems built of Synchronous Dynamic Random Access Memory with Double Data Rate (SDRAM-DDR) elements.Type: GrantFiled: February 6, 2002Date of Patent: June 13, 2006Assignee: International Business Machines CorporationInventors: Paul William Coteus, William Paul Hovis, William Wu Shen, Toshiaki Kirihata
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Patent number: 6941414Abstract: The invention provides a simple interface circuit between a large capacity, high speed DRAM and a single port SRAM cache to achieve fast-cycle memory performance. The interface circuit provides wider bandwidth internal communications than external data transfers. The interface circuit schedules parallel pipeline operations so that one set of data buses can be shared in cycles by several data flows to save chip area and alleviate data congestion. A flexible design is provided that can be used for a range of bandwidths of data transfer and generally any size bandwidth ranging from 32 to 4096 bits wide can use this same approach.Type: GrantFiled: May 15, 2001Date of Patent: September 6, 2005Assignee: International Business Machines CorporationInventors: Louis L. Hsu, William Wu Shen, Li-Kong Wang
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Patent number: 6674684Abstract: A memory chip and a method of operating a chip with a number of banks of memory to be backward compatible with a controller designed to operate a chip having a lesser number of banks. To accomplish this, a control (bit) is produced on the chip Mode Register Set (MRS) that activates corresponding logic in the chip to move one of the bits used to address a memory cell, such as one of the row address bits, to a position of the bank ID field. This provides a greater number of bank ID bits to select memory banks of a chip so that a high number bank chip can accept a command supplied by a controller designed to operate a chip with a fewer number of banks and that has a format of a lesser number of bank ID bits.Type: GrantFiled: June 11, 2003Date of Patent: January 6, 2004Assignee: Infineon Technologies North America Corp.Inventor: William Wu Shen
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Patent number: 6519736Abstract: Uncorrectable errors are isolated to one component of a computing system comprising a plurality of components. First, upon detection of an uncorrectable error, a special check bit pattern is generated. This check bit pattern is used to indicate the occurrence of an uncorrectable error, as well as the location of the occurrence of the error. Subsequently, the check bit pattern is incorporated into the data word being transmitted, and thus may be used to isolate an uncorrectable error to the exact location of occurrence.Type: GrantFiled: November 30, 1999Date of Patent: February 11, 2003Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
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Publication number: 20020174291Abstract: The invention provides a simple interface circuit between a large capacity, high speed DRAM and a single port SRAM cache to achieve fast-cycle memory performance. The interface circuit provides wider bandwidth internal communications than external data transfers. The interface circuit schedules parallel pipeline operations so that one set of data buses can be shared in cycles by several data flows to save chip area and alleviate data congestion. A flexible design is provided that can be used for a range of bandwidths of data transfer and generally any size bandwidth ranging from 32 to 4096 bits wide can use this same approach.Type: ApplicationFiled: May 15, 2001Publication date: November 21, 2002Applicant: International Business Machines CorporationInventors: Louis L. Hsu, William Wu Shen, Li-Kong Wang
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Patent number: 6463563Abstract: An error correction code for single symbol error correction and double symbol error detection is generated according to a novel modular H-matrix. The H-matrix utilizes a modular design with multiple iterations of a plurality of subsets. In particular, one example of this H-matrix includes a plurality of rows and columns with each of at least one row of the H-matrix comprising, in part, multiple iterations of one subset of the plurality of subsets. The remainder of the rows, comprises, in part, a cyclic permutation of all of the remaining subsets of the plurality of subsets.Type: GrantFiled: November 30, 1999Date of Patent: October 8, 2002Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
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Patent number: 6460157Abstract: Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.Type: GrantFiled: November 30, 1999Date of Patent: October 1, 2002Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
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Patent number: 6457154Abstract: Uncorrectable errors are detected during the transmission of a data word according to an error correction code. Then, any address faults are identified from among the detected uncorrectable errors. In addition, address faults as well as uncorrectable memory data failures are detected from among the detected uncorrectable errors. Furthermore, address parity bits are not required to be stored to memory.Type: GrantFiled: November 30, 1999Date of Patent: September 24, 2002Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
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Publication number: 20020108013Abstract: The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array.Type: ApplicationFiled: February 6, 2002Publication date: August 8, 2002Inventors: Paul William Coteus, William Paul Hovis, William Wu Shen, Toshiaki Kirihata
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Patent number: 6182174Abstract: A memory interface between the storage controller and memory card of an S/390 system uses the S/390 Storage Protect (SP) Key as an indication or protocol of storage command acceptance by the memory card. When the SP key is returned, then the command is deemed to be accepted by the memory card and the key will be used by the processor for its storage validation in accordance with the S/390 architecture. In the event that the memory card detected an error associated with the command, it will then return an error response code via a memory status bus. The memory status bus is multiplexed to service the existing architected requirement as well as an indicator of handshaking between the memory controller and the memory card.Type: GrantFiled: April 13, 1998Date of Patent: January 30, 2001Assignee: International Business Machines CorporationInventors: Kevin W. Kark, William Wu Shen, Russell W. Lavallee, Udo Wille, Hartmut Ulland, Walter Lipponer
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Patent number: 6163857Abstract: A computer system having central processors (CPs), an associated L2 cache, and processor memory arrays (PMAs), is provided with store logic and and fetch logic used to detect and correct data errors and to write the resulting data the associated cache. The store logic and and fetch logic blocks UEs from the cache for CP stores, for PMA (mainstore) fetches/loads, and for cache-to-cache loads, and with uncorrectable error recovery cache fetch and store logic injects `Special UEs` into the cache when loads cannot be blocked and abends CP jobs for UEs during CP stores, for UEs from PMA, for UEs from remote cache, and for UEs from local cache.Type: GrantFiled: April 30, 1998Date of Patent: December 19, 2000Assignee: International Business Machines CorporationInventors: Patrick James Meaney, Pak-kin Mak, William Wu Shen, Gary Eugene Strait
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Patent number: 6052772Abstract: A memory request protocol allows a memory request to be withdrawn or "cancelled" without penalty so no memory resource is wasted in doing so during an assigned "cancel window". When the memory card starts to process a command from the memory controller, for a predefined number of cycles a period of time is available where the memory card can't accept another command due to a resource conflict. This provides an opportunity to re-balance requests to the memory controller in this period of time or "cancel window".Type: GrantFiled: April 13, 1998Date of Patent: April 18, 2000Assignee: International Business Machines CorporationInventors: Kevin W. Kark, William Wu Shen, George C. Wellwood
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Patent number: 6047361Abstract: A memory control device, having a common synchronous interface coupled thereto, for accessing asynchronous memory devices, as well as other synchronous devices. The memory control device receives, via the synchronous interface, a command having a synchronous format, and translates at least a portion of the command from the synchronous format to an asynchronous format. The command in the asynchronous format is then used to access an asynchronous memory device. The asynchronous memory device can have one of various formats, each of which is supported by the memory control device. The memory control device emulates synchronous memory devices for the system memory controller coupled to the memory control device, even when asynchronous devices are accessed. The memory control device can also translate commands from one synchronous format to another synchronous format such that memory devices of the another synchronous format can be accessed.Type: GrantFiled: August 21, 1996Date of Patent: April 4, 2000Assignee: International Business Machines CorporationInventors: Giacomo Vincent Ingenio, Russell William Lavallee, William Wu Shen
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Patent number: 5768294Abstract: An apparatus and method is discussed using a parity check matrix in order to acheive correction and detection of errors particularly pertaining to detection data fetched from a wrong address. The code structure enhances utilization of chip reliability by encoding and decoding digital signals through the utilization of a parity check matrix and parity bits generated from system address bits of a computer system with k symbols and b bits per symbol.Type: GrantFiled: December 11, 1995Date of Patent: June 16, 1998Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen
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Patent number: 5761221Abstract: A method and apparatus for performing digital signal error detection and correction through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received. Errors are corrected and detected through assignment of data bits to different modules in a memory of a computer system having symbols which are b bits in length.Type: GrantFiled: December 11, 1995Date of Patent: June 2, 1998Assignee: International Business Machines CorporationInventors: Klaus Ruediger Baat, Chin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen