Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.

Abstract: A computing circuit is configured to perform a bit-serial multiplication of an input signal and a weight signal. A multiplier circuit is configured to receive the input signal and the weight signal and to provide a product sum. An adder circuit is configured to receive the product sum and to provide a partial sum. A partial sum register is configured to: clock-gate a second part of the partial sum register; receive the partial sum; provide, based on the partial sum, a first output of the bit-serial multiplication through a first part of the partial sum register; determine whether not to clock-gate the second part of the partial sum register or not based on a first feature bit of the partial sum; and provide, based on the first feature bit of the partial sum, a second output of the bit-serial multiplication through the second part of the partial sum register.

Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Abstract: Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.

Abstract: A circuit includes local computing cells. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a first data type, a first sum including (i) a first product of a first input data element and a first weight data element; and (ii) a second product of a second input data element and a second weight data element. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a second data type, (i) a second sum of a first portion of a third input data element and a first portion of a third weight data element; and (ii) a third product of a second portion of the third input data element and a second portion of the third weight data element.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.

Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.

Abstract: The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.

Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.

Abstract: Embodiment described herein provide systems, apparatuses and methods for convoluting a filter (“kernel”) to input data in the form of an input array by reusing computations of repeated data entries in the input array due to convolution movements from one convolution step to the next. In one embodiment, to compute a convolution of an input matrix and a filter matrix, instead of unrolling data entries from the input matrix of each convolution step into an input vector, only non-repeated new data entries at each convolution step may be added to the input vector. An input mapping circuit that implements an input parameter mapping matrix may then iteratively map data entries of the input vector to different weight registers that corresponds to weights in the filter matrix.

Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Abstract: Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.

Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.

Abstract: Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.

Abstract: An integrated circuit includes a memory storage having bit cells, a write path switch configured to have a connection state determined by a reliability indicator, and a write driver having an input configured to receive an input data from a write terminal through either a first write path or a second write path. The input data received through the first write path is configured to be equal to the data at the write terminal, and the input data received through the second write path is configured to be a bitwise complement of the data at the write terminal. The reliability indicator is configured to be set based on a majority bit value in the data or based on a minority bit value in the data.

Abstract: A memory device includes a set of word lines, first and second sets of bit lines, a first source line having first and second source line contacts, first and second strings of transistors electrically coupled in parallel between the first and second source line contacts of the source line, and first and second sets of data storage elements. Each word line in the set of word lines is electrically coupled to gates of a transistor in the first string and a corresponding transistor in the second string. The first set of data storage elements is electrically coupled between the first string of transistors and the first set of bit lines. The second set of data storage elements is electrically coupled between the second string of transistors and the second set of bit lines.

Abstract: A system includes a memory cell array including multi-level cells, an input data scramble circuit configured to receive input data and match lower error tolerant bits with higher error tolerant bits to provide matched bit sets, wherein each of the matched bit sets includes at least one lower error tolerant bit and at least one higher error tolerant bit, and a write driver configured to receive the matched bit sets and store each of the matched bit sets into one memory cell of the multi-level cells.

Abstract: An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

Abstract: A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.