Abstract: An encode apparatus and an encode method may be provided. The encoding apparatus may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

Abstract: A system includes a memory cell array including multi-level cells, an input data scramble circuit configured to receive input data and match lower error tolerant bits with higher error tolerant bits to provide matched bit sets, wherein each of the matched bit sets includes at least one lower error tolerant bit and at least one higher error tolerant bit, and a write driver configured to receive the matched bit sets and store each of the matched bit sets into one memory cell of the multi-level cells.

Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

Abstract: A method of storing a data into a memory storage having bit cells. The method includes identifying each of the binary one and the binary zero in the data as either a majority bit value or a minority bit value based on the probability of finding the binary one in the data or based on the probability of finding the binary zero in the data. In the method, a bit of the data is stored into the bit cell as the more preferred state if the bit of the data has the majority bit value, and a bit of the data is stored into the bit cell as the less preferred state if the bit of the data has the minority bit value.

Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.

Abstract: An integrated chip has an array of memory cells disposed over a semiconductor substrate and a driver circuit. The driver circuit provides the array with a read voltage that varies in relation to an approximate temperature of the memory array to ameliorate temperature dependencies in read currents. The driver circuit may vary the read voltage in an inverse relationship with temperature. The read voltage may be varied continuous or stepwise and the driver circuit may use a table lookup. Optionally, the driver circuit measures a current and modulates the read voltage until the current is within a target range. The memory cells may be multi-level phase change memory cells that include a plurality phase change element disposed between a bottom electrode and a top electrode. Modulating the read voltage to reduce temperature-dependent current variations is particularly useful for multi-level cells.

Abstract: A memory device and a method of correcting error in a memory device is provided. The memory device controller includes a memory array, a tie-breaker array, a write controller, a verify circuit, and a controller. The memory array includes a plurality of memory cells. The tie-breaker array includes a plurality of tie-breaker rows. The write controller is configured to apply a programming voltage to the memory array. The verify circuit is configured to apply a verify voltage to verify whether the memory cells in the memory array are in an unambiguous state or not. The controller is configured to enable one or more tie-breaker rows in additions to the memory array to adjust an output of the memory array when the memory cells in the memory array are in an ambiguous state.

Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Abstract: A method includes: generating a first difference between a first resistance value of a first memory cell and a first predetermined resistance value; generating a first signal based on the first difference; applying the first signal to the first memory cell to adjust the first resistance value; and after the first signal is applied to the first memory cell, comparing the first resistance value and the first predetermined resistance value, to further adjust the first resistance value until the first resistance value reaches the first predetermined resistance value. A memory device is also disclosed herein.

Abstract: A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.

Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Abstract: A memory device and a method of correcting error in a memory device is provided. The memory device controller includes a memory array, a tie-breaker array, a write controller, a verify circuit, and a controller. The memory array includes a plurality of memory cells. The tie-breaker array includes a plurality of tie-breaker rows. The write controller is configured to apply a programming voltage to the memory array. The verify circuit is configured to apply a verify voltage to verify whether the memory cells in the memory array are in an unambiguous state or not. The controller is configured to enable one or more tie-breaker rows in additions to the memory array to adjust an output of the memory array when the memory cells in the memory array are in an ambiguous state.

Abstract: A method includes: applying a first signal to memory cells in a memory device, to adjust resistance values of the memory cells; after applying the first signal, applying a second signal to the memory cells other than a first memory cell in the memory cells, to further adjust the resistance values of the memory cells other than the first memory cell. A memory device is also disclosed herein.

Abstract: A random number generator that includes control circuit, an oscillation circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The oscillation circuit generates an oscillation signal based on the configuration of the bias control signal. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.

Abstract: A memory device and a method of correcting error in a memory device is provided. The memory device controller includes a memory array, a tie-breaker array, a write controller, a verify circuit, and a controller. The memory array includes a plurality of memory cells. The tie-breaker array includes a plurality of tie-breaker rows. The write controller is configured to apply a programming voltage to the memory array. The verify circuit is configured to apply a verify voltage to verify whether the memory cells in the memory array are in an unambiguous state or not. The controller is configured to enable one or more tie-breaker rows in additions to the memory array to adjust an output of the memory array when the memory cells in the memory array are in an ambiguous state.

Abstract: Various embodiments provide methods for configuring a phase-change random-access memory (PCRAM) structures, such as PCRAM operating in a single-level-cell (SLC) mode or a multi-level-cell (MLC) mode. Various embodiments may support a PCRAM structure being operating in a SLC mode for lower power and a MLC mode for lower variability. Various embodiments may support a PCRAM structure being operating in a SLC mode or a MLC mode based at least in part on an error tolerance for a neural network layer.

Abstract: An integrated chip has an array of memory cells disposed over a semiconductor substrate and a driver circuit. The driver circuit provides the array with a read voltage that varies in relation to an approximate temperature of the memory array to ameliorate temperature dependencies in read currents. The driver circuit may vary the read voltage in an inverse relationship with temperature. The read voltage may be varied continuous or stepwise and the driver circuit may use a table lookup. Optionally, the driver circuit measures a current and modulates the read voltage until the current is within a target range. The memory cells may be multi-level phase change memory cells that include a plurality phase change element disposed between a bottom electrode and a top electrode. Modulating the read voltage to reduce temperature-dependent current variations is particularly useful for multi-level cells.

Abstract: A random number generator that includes control circuit, an oscillation circuit, a dynamic header circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The dynamic header circuit generates a bias voltage based on the configuration of the bias control signal. The oscillation circuit generates an oscillation signal based on the bias voltage. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.

Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.

Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.