Abstract: Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device.

Abstract: A memory circuit comprises a D/A converter connected with an input/output circuit and with a writing circuit, wherein the D/A converter converts a digital data with at least two digital bits received from the input/output circuit to one analog value and forwards the analog value to the writing circuit, wherein the digital data is at least a part of a floating point number, wherein the writing circuit writes the analog value in at least one selected memory cell, and an A/D converter connected with a reading circuit and with the input/output circuit, wherein the reading circuit reads an analog value from a selected memory cell and forwards the analog value to the A/D converter, wherein the A/D converter converts the analog value to digital data, and wherein the A/D converter forwards the digital data to the input/output circuit.

Abstract: One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator.

Abstract: The invention relates to a semiconductor memory device, which can be operated in a normal operating mode and a test mode, comprising: data terminals and data clock terminals; input receivers for processing the signal arriving via the respective terminal, a respective input receiver being assigned to a data terminal and/or data clock terminal; at least one test circuit, a respective test circuit being assigned to an input receiver and the test circuit being designed for determining at least one predetermined property of the assigned input receiver.

Abstract: A method comprises the step of obtaining a first signal of the signal from a first position of a transmission channel, and a second signal of the signal from a second position of the transmission channel, determining a delay time between the first signal and the second signal by a first degree of alikeness of the first signal and the second signal trace, and determining a direction function vector of the signal by a second degree of alikeness of the first signal and the second signal trace.

Abstract: Method of controlling a driver strength and a termination impedance of a signal line of an interface, wherein the driver sends an output signal as an alternating voltage with a frequency, wherein the signal line is terminated with a termination impedance, wherein the driver strength is changed depending on a changing of the frequency of the output signal.

Abstract: A method for checking the refresh function of a memory having a refresh device includes the steps of, first, ascertaining whether or not refresh request pulses are being produced on the information memory and, if so, at what intervals of time from one another these refresh request pulses are produced. Next, a control unit for the information memory is supplied with refresh test pulses produced outside of the information memory instead of being supplied with the refresh request pulses. Then, the refresh test pulses are used to check a refresh device situated on the information memory.

Abstract: A device for reducing mutual crosstalk of a signal routed across a first line and a second signal routed across a second line, wherein by the mutual crosstalk at an output of the first line a first interfered signal may be obtained and at an output of the second line a second interfered signal may be obtained, comprising a modifier for modifying the first interfered signal that is interfered by crosstalk due to the second signal, and for modifying the second interfered signal that is interfered by crosstalk due to the first signal, wherein the modifier is adapted to model an interference due to the mutual crosstalk, and a combiner for combining the first interfered signal with the modified second interfered signal to obtain a first corrected signal and for combining the second interfered signal with the modified first interfered signal to obtain a second corrected signal.

Abstract: A device and method for performing a test of semiconductor devices with an optical interface. In one embodiment, the device performs a test at a semiconductor device with an integrated self test function and with an optical interface. An optical transmitter and an optical receiver provide a system configured for returning an optical emission of the semiconductor device from the optical transmitter to the optical receiver of the semiconductor device.

Abstract: Methods and apparatus for storing data in different regions of the memory device based on, for example, a reliability requirement of the data. A memory controller may determine a category for data, for example, high reliability data and low reliability data, prior to storing the data in memory. The data may be stored in a region of memory associated with the category of data according to a method associated with the category of data. For example, high reliability data may be stored in a particular region of memory using lower clock frequencies, with additional error correction bits, and/or at multiple redundant locations. In contrast, low reliability data may be stored other regions of the memory using higher clock frequencies, without additional error correction bits and/or at singular locations (i.e., without redundant locations.

Abstract: A method and apparatus for accessing one or more memory devices using an optical multi-mode signal. The method includes providing an optical multi-mode signal including a first mode and a second mode and transmitting the optical multi-mode signal via an optical multi-mode bus to the one or more memory devices. The first mode is used to perform a first access to the one or more memory devices and the second mode is used to perform a second access to the one or more memory devices.

Abstract: A method and apparatus for accessing a memory device. The method includes providing control signals for an access command to the memory device via an asynchronous interface and transmitting data for the access command to the memory device. The method also includes encoding, into the transmitted data, a clock signal. The encoded clock signal in the transmitted data is used by the memory device for receiving the data transmission.

Abstract: The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and encompassing an output driver, input driver, and data pads. The method includes the steps of communicating test input data to be used for a test to the memory device, performing a test using the test input data in order to obtain test output data, the test data read out being passed via an output driver, at least one data pad, and an input driver, wherein the input drivers and output drivers are switched during the test in such a way as to enable data to be simultaneously read from and written to the memory device, and creating a data test result from the test output data. Furthermore, the invention relates to a memory device and a system for testing a memory device.

Abstract: A display having a screen, and memory for storing picture data is disclosed. In one embodiment, the screen includes a plurality of pixels, the pixels in a first mode of the display being controlled by the picture data stored in the memory, and in a second mode of the display being controlled by picture data received from an external processing unit.

Abstract: Method and apparatus for refreshing selective memory cells. A refresh circuit is connected with the memory cells and operates to refresh data stored in the memory cells on the basis of the values of valid bits having a predefined association with the memory cells.

Abstract: A memory circuit comprises a D/A converter connected with an input/output circuit and with a writing circuit, wherein the D/A converter converts a digital data with at least two digital bits received from the input/output circuit to one analog value and forwards the analog value to the writing circuit, wherein the digital data is at least a part of a floating point number, wherein the writing circuit writes the analog value in at least one selected memory cell, and an A/D converter connected with a reading circuit and with the input/output circuit, wherein the reading circuit reads an analog value from a selected memory cell and forwards the analog value to the A/D converter, wherein the A/D converter converts the analog value to digital data, and wherein the A/D converter forwards the digital data to the input/output circuit.

Abstract: A method of sending data on request from a memory to a device, wherein the memory receives a request from the device for sending predetermined data to the device, wherein the memory sends data and information about the data to the device.

Abstract: A method and system comprising at least two processing units that are connected with at least two memory units, wherein first data buses are connected with the memory units, wherein second data buses are connected with processing units, wherein cross bar switches are disposed between first and second data buses, and wherein a control unit controls the cross bar switches for connecting selected processing units with selected memory units.

Abstract: Memory with at least two memory banks each having memory cells, a control circuit, and at least one bank mode register, wherein the bank mode register stores information about an operation mode of a memory bank, wherein the control circuit operates at least one of the memory banks according to the information of the mode register.

Abstract: Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked out of the testing interface and to the DUT according to the test clock signal. Further, the test clock signal is delayed by a period of time and then a delayed clock signal is issued to the device. The data previously written to the DUT is read out of the DUT and compared with the test data received from the external test apparatus. The period of time by which the test clock signal is delayed can be varied to achieve a desired timing.