Abstract: A method for testing the refresh device of an information memory contains the following: a refresh selector for selecting memory cells to be refreshed; a sensor for sensing the state of each cell selected by the selector and a restorer for setting each selected cell into a fresh state, which, in a refresh operating mode of the restorer which effects the refreshing, represents the information derived from the sensed state. According to the invention, at the beginning of the test, the states of the cells that are to participate in the test are verified and before the elapsing of the guaranteed minimum retention time of the memory cells after this verification, the restorer is operated in a test operating mode in which the fresh state that it is to set for each participating cell is in each case a predetermined state which differs perceptively from the previously verified state.

Abstract: In order to be able to carry out the testing of integrated semiconductor memory devices particularly rapidly, it is proposed that the test result data of the respective memory area which are obtained in the area of the semiconductor memory device are formed, transmitted and/or stored externally in each case as a plurality of blockwise test result lists.

Abstract: A method for checking the refresh function of a memory having a refresh device includes the steps of, first, ascertaining whether or not refresh request pulses are being produced on the information memory and, if so, at what intervals of time from one another these refresh request pulses are produced. Next, a control unit for the information memory is supplied with refresh test pulses produced outside of the information memory instead of being supplied with the refresh request pulses. Then, the refresh test pulses are used to check a refresh device situated on the information memory.

Abstract: To carry out a refresh operation, a semiconductor memory having dynamic memory cells includes a sense amplifier that, on the output side, provides a signal depending on a control of a bit line driver. The bit line driver is embodied as an adiabatic amplifier, preferably, having current paths through which charges that are to be exchanged during a charge-reversal operation are buffer-stored in capacitors. Power loss for the charge reversal of the bit line capacitances is thereby saved. A method for operating the memory is also provided.

Abstract: A method and a configuration for the output of bit error tables from semiconductor devices are described. A test control unit reads the bit error table from the memory device following a request from the test apparatus. Then, the bit error tables are transmitted sequentially to the test apparatus for further processing.

Abstract: An electrical circuit can be described with a reference model that has a plurality of states and a plurality of state transitions. Acceptable and/or unacceptable instruction sets are predefined for each state. Acceptable and unacceptable instruction sets are generated randomly in succession from the reference model and applied to a mapping of the electrical circuit for processing. By comparing the instruction sets processed by the mapping of the electrical circuit with the instruction sets determined from the reference model, conclusive information relating to the mapping of the electrical circuit is obtained.

Abstract: In order to be able to carry out the testing of integrated semiconductor memory devices particularly rapidly, it is proposed that the test result data of the respective memory area which are obtained in the area of the semiconductor memory device are formed, transmitted and/or stored externally in each case as a plurality of blockwise test result lists.

Abstract: An address generator for generating addresses for an on-chip trim circuit for tuning a reference voltage produced on a semiconductor chip. The address generator contains a particular number of stages, each made up of a memory latch, which, upon a control signal supplied to a control input of the address generator, and upon a clock signal applied to a clock input of the address generator, can optionally be operated as a synchronous counter or as a shift register. The number M being greater than or equal to 1.

Abstract: To carry out a refresh operation, a semiconductor memory having dynamic memory cells includes a sense amplifier that, on the output side, provides a signal depending on a control of a bit line driver. The bit line driver is embodied as an adiabatic amplifier, preferably, having current paths through which charges that are to be exchanged during a charge-reversal operation are buffer-stored in capacitors. Power loss for the charge reversal of the bit line capacitances is thereby saved. A method for operating the memory is also provided.

Abstract: The temperature of a semiconductor component is determined by way of a memory cell that includes a transistor and a capacitor. To that end, a signal is determined in dependence on a threshold voltage of the transistor and a value for the temperature of the transistor is determined in dependence on the signal.

Abstract: A method and device for measuring voltage of an internal reference voltage source of an integrated semiconductor circuit, in particular, a DRAM, including the steps of comparing a reference voltage to an external comparison voltage with a comparator, forming a measured value for the reference voltage to be set in accordance with a comparison result, switching a commutator by a clock- or software-control to alternatively apply the reference voltage and the comparison voltage to the comparator inputs at the same time, varying one of the reference and comparison voltage to a setpoint voltage value until the comparator output changes its logic value at each commutator switched stage, buffering the voltage values present for each switched state when the logic value changes, forming an average value for the reference voltage from the stored voltage values, and setting the reference voltage as a function of the average value formed.

Abstract: An address generator for generating addresses for an on-chip trim circuit for tuning a reference voltage produced on a semiconductor chip. The address generator contains a particular number of stages, each made up of a memory latch, which, upon a control signal supplied to a control input of the address generator, and upon a clock signal applied to a clock input of the address generator, can optionally be operated as a synchronous counter or as a shift register. The number M being greater than or equal to 1.

Abstract: A method for testing the refresh device of an information memory contains the following: a refresh selector for selecting memory cells to be refreshed; a sensor for sensing the state of each cell selected by the selector and a restorer for setting each selected cell into a fresh state, which, in a refresh operating mode of the restorer which effects the refreshing, represents the information derived from the sensed state. According to the invention, at the beginning of the test, the states of the cells that are to participate in the test are verified and before the elapsing of the guaranteed minimum retention time of the memory cells after this verification, the restorer is operated in a test operating mode in which the fresh state that it is to set for each participating cell is in each case a predetermined state which differs perceptively from the previously verified state.