Patents by Inventor Won-Joon Choi

Won-Joon Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190198261
    Abstract: A method of synthesizing multi-shell structure nanoparticles includes uniformly distributing core nanoparticles to a first porous fuel membrane, coating the core nanoparticles fixed to the first porous fuel membrane with a fuel, and combusting the fuel coated on the core nanoparticles and the first porous fuel membrane to coat a first carbon film on surfaces of the core nanoparticles.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 27, 2019
    Inventors: Won-joon CHOI, Tae-han YEO, Dong-joon SHIN
  • Publication number: 20190189907
    Abstract: This technology provides a method for fabricating an electronic device. A method for fabricating an electronic device including a variable resistance element, which includes a free layer having a variable magnetization direction; a pinned layer having a first non-variable magnetization direction, and including first ferromagnetic materials and a first spacer layer interposed between adjacent two first ferromagnetic materials among the first ferromagnetic materials; a tunnel barrier layer interposed between the free layer and the pinned layer; a magnetic correction layer having a second magnetization direction which is anti-parallel to the first magnetization direction; and a third spacer layer interposed between the magnetic correction layer and the pinned layer, and providing an anti-ferromagnetic exchange coupling between the magnetic correction layer and the pinned layer.
    Type: Application
    Filed: November 19, 2018
    Publication date: June 20, 2019
    Inventors: Guk-Cheon Kim, Yang-Kon Kim, Seung Mo Noh, Won-Joon Choi
  • Patent number: 10305030
    Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
  • Publication number: 20190109280
    Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 11, 2019
    Inventors: Jong-Koo LIM, Won-Joon CHOI, Guk-Cheon KIM, Yang-Kon KIM, Ku-Youl JUNG, Toshihiko NAGASE, Youngmin EEH, Daisuke WATANABE, Kazuya SAWADA, Makoto NAGAMINE
  • Publication number: 20190081066
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Application
    Filed: April 24, 2018
    Publication date: March 14, 2019
    Inventors: Won Joon CHOI, Min Sung KO, Kyeong Bae KIM, Jong Gi KIM, Dong Sun SHEEN, Jung Myoung SHIM, Young Ho YANG, Hyeng Woo EOM, Kwang Wook LEE, Woo Jae CHUNG
  • Publication number: 20190079873
    Abstract: An electronic device includes semiconductor memory, the semiconductor memory including an under layer; a first magnetic layer located over the under layer and having a variable magnetization direction; a tunnel barrier layer located over the first magnetic layer; and a second magnetic layer located over the tunnel barrier layer and having a pinned magnetization direction, wherein the under layer includes a first metal nitride layer having a NaCl crystal structure and a second metal nitride layer containing a light metal.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 14, 2019
    Inventors: Yang-Kon KIM, Ki-Seon PARK, Bo-Mi LEE, Won-Joon CHOI, Guk-Cheon KIM, Daisuke WATANABE, Makoto NAGAMINE, Young-Min EEH, Koji UEDA, Toshihiko NAGASE, Kazuya SAWADA
  • Publication number: 20190052302
    Abstract: This disclosure provides techniques for managing antenna sharing on a multi-mode wireless device between coexisting cellular and WLAN modems operating on the same band. One of the modems can communicate a WLAN scanning parameter to another one of the modems, and the distribution of shared antennas between the cellular modem and the WLAN modem may be modified based at least in part on the communicated scanning parameter to accommodate a WLAN scan on channels in the shared band. The distribution of the shared antennas between the modems for the WLAN scan may additionally or alternatively be selected based at least in part on the source of a detected WLAN scanning trigger (e.g., whether the scan is triggered by an application of the wireless device or the WLAN modem of the wireless device).
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Inventors: Heechoon Lee, Won-Joon Choi, Ning He
  • Patent number: 10203380
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 12, 2019
    Assignees: SK Hynix Inc., Toshiba Memory Corporation
    Inventors: Ku-Youl Jung, Guk-Cheon Kim, Toshihiko Nagase, Daisuke Watanabe, Won-Joon Choi, Youngmin Eeh, Kazuya Sawada
  • Patent number: 10170691
    Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: January 1, 2019
    Assignees: SK Hynix Inc., TOSHIBA MEMORY CORPORATION
    Inventors: Jong-Koo Lim, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh, Daisuke Watanabe, Kazuya Sawada, Makoto Nagamine
  • Patent number: 10149130
    Abstract: A method of outputting notification of data reception in a device configured to transmit and receive data to and from an external device and a computer program recorded on a non-transitory computer-readable recording medium, which when executed by a processor, is configured to cause the device to perform the method are provided. The method includes receiving, by a processor of the device, data from the external device, determining, by the processor of the device, an importance of notification by recognizing at least one of a state of the device and surrounding circumstances of the device, and outputting. by the processor of the device, the notification of the data reception when the determined importance of the notification exceeds a first threshold value.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: December 4, 2018
    Assignee: Line Corporation
    Inventor: Won Joon Choi
  • Patent number: 10133689
    Abstract: This technology provides a method for fabricating an electronic device. A method for fabricating an electronic device including a variable resistance element, which includes a free layer having a variable magnetization direction; a pinned layer having a first non-variable magnetization direction, and including first ferromagnetic materials and a first spacer layer interposed between adjacent two first ferromagnetic materials among the first ferromagnetic materials; a tunnel barrier layer interposed between the free layer and the pinned layer; a magnetic correction layer having a second magnetization direction which is anti-parallel to the first magnetization direction; and a third spacer layer interposed between the magnetic correction layer and the pinned layer, and providing an anti-ferromagnetic exchange coupling between the magnetic correction layer and the pinned layer.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: November 20, 2018
    Assignee: SK hynix Inc.
    Inventors: Guk-Cheon Kim, Yang-Kon Kim, Seung Mo Noh, Won-Joon Choi
  • Patent number: 10134458
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 20, 2018
    Assignee: SK hynix Inc.
    Inventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Jong-Koo Lim
  • Patent number: 10122406
    Abstract: This disclosure provides techniques for managing antenna sharing on a multi-mode wireless device between coexisting cellular and WLAN modems operating on the same band. One of the modems can communicate a WLAN scanning parameter to another one of the modems, and the distribution of shared antennas between the cellular modem and the WLAN modem may be modified based at least in part on the communicated scanning parameter to accommodate a WLAN scan on channels in the shared band. The distribution of the shared antennas between the modems for the WLAN scan may additionally or alternatively be selected based at least in part on the source of a detected WLAN scanning trigger (e.g., whether the scan is triggered by an application of the wireless device or the WLAN modem of the wireless device).
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 6, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Heechoon Lee, Won-Joon Choi, Ning He
  • Patent number: 10120799
    Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: November 6, 2018
    Assignee: SK hynix Inc.
    Inventors: Cha-Deok Dong, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim
  • Patent number: 10114422
    Abstract: A cover panel and a display device, the cover panel including a heat sink layer; an impact absorbing layer on the heat sink layer; and an elastic pattern on at least one side of the impact absorbing layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 30, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Chan Lee, Jong Deok Park, Byung Wook Ahn, Ki Kyung Youk, Jee Hun Lim, Suk Won Jung, Won Joon Choi, Jeong Ho Hwang
  • Patent number: 10103318
    Abstract: According to one embodiment, there is provided a magnetoresistive element, including a first magnetic layer, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer, wherein one of the first and second magnetic layers include one of Co and Fe, and a material having a higher standard electrode potential than Co and Fe.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 16, 2018
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX, INC.
    Inventors: Daisuke Watanabe, Yang Kon Kim, Makoto Nagamine, Youngmin Eeh, Koji Ueda, Toshihiko Nagase, Kazuya Sawada, Guk Cheon Kim, Bo Mi Lee, Won Joon Choi
  • Publication number: 20180284199
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.
    Type: Application
    Filed: December 14, 2017
    Publication date: October 4, 2018
    Inventors: Ku-Youl JUNG, Guk-Cheon KIM, Toshihiko NAGASE, Daisuke WATANABE, Won-Joon CHOI, Youngmin EEH, Kazuya SAWADA
  • Patent number: 10090503
    Abstract: Disclosed herein is an electrode terminal connecting member to connect two or more battery cells in series and/or in parallel to each other so as to manufacture a battery cell core pack, wherein the electrode terminal connecting member includes a plate body having a size sufficient to connect electrode terminals of the battery cells arranged in at least 2×2 matrix to each other, and the electrode terminals of the battery cells are directly coupled to the plate body in a state in which the plate body is not bent.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: October 2, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Won Joon Choi, Youngsun Park, SooRyoung Kim, Ho Yeong Yang, Seunghyun Bang, Kwang woo Nam
  • Patent number: 10079399
    Abstract: A fuel cell using biogas as a fuel is provided, in which the fuel cell is supplied with a first gas required at a fuel electrode and a second gas required at an air electrode, which are separated from the biogas by a selective permeation method using a separation membrane of a gas-purification separation unit, and supplies gas discharged from the fuel cell along with the biogas to the gas-purification separation unit.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: September 18, 2018
    Assignee: DOOSAN HEAVY INDUSTRIES & CONSTRUCTION CO., LTD.
    Inventors: Choa Mun Yun, Sung Hoon Kim, Won Joon Choi, In Gab Chang
  • Patent number: 10062424
    Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: August 28, 2018
    Assignee: SK hynix Inc.
    Inventors: Yang-Kon Kim, Guk-Cheon Kim, Jeong-Myeong Kim, Jong-Koo Lim, Ku-Youl Jung, Won-Joon Choi