Abstract: A ballast water treatment apparatus for a ship includes a water collection part for collecting sea water, a forward osmosis process unit for producing ballast water and treatment water obtained by desalinating the sea water collected through the water collection part, and a ballast water tank for storing the ballast water produced by the forward osmosis process unit. Since the sea water is treated using a forward osmosis process, fresh water required within the ship can be supplied and the treated sea water can be used as ballast water. In addition, since waste heat and carbon dioxide generated in the ship are used to treat the sea water, the ballast water can be treated and produced in a low-cost and high efficient manner.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an interface enhancement layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface enhancement layer may include an Fe-rich first layer; a Co-rich second layer formed over the first layer; and a metal layer formed over the second layer.

Abstract: Implementations of the disclosed technology provide an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a magnetic tunnel junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer sandwiched between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer includes a first under layer including a silicon-based alloy, and a second under layer located on the first under layer and including a metal.

Abstract: According to one embodiment, a magnetic memory includes a first magnetic layer, a second magnetic layer, a non-magnetic intermediate layer provided between the first magnetic layer and the second magnetic layer and an underlying layer provided on an opposite side of the first magnetic layer with respect to the intermediate layer, and the underlying layer contains AlN of a hcp structure.

Abstract: Certain aspects of the present disclosure relate to methods and apparatus for wireless communication, and more particularly, to methods and apparatus that utilize one or more user equipment (UE) panic states under connected discontinuous reception (C-DRX) mode in long term evolution (LTE).

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.

Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Abstract: Certain aspects of the present disclosure generally relate to wireless communications. In some aspects, a wireless communication device may determine that the wireless communication device is configured to use a primary component carrier (PCC), a first secondary component carrier (SCC), and a second SCC for carrier aggregation. A primary cell may be associated with the PCC, a first secondary cell may be associated with the first SCC, and a second secondary cell may be associated with the second SCC. The first secondary cell may provide control information for the second secondary cell. The wireless communication device may monitor at least one of the first SCC or the second SCC. The wireless communication device may perform an action associated with the second secondary cell based, at least in part, on monitoring the at least one the first SCC or the second SCC.

Abstract: In a semi-open loop rate adaptation scheme for a multiple-input multiple-output (MIMO) system, a transmitter can advantageously use one or more quality metrics of an uplink as well as knowledge of device characteristics of both ends to perform fast and accurate rate adaptation.

Abstract: A cover panel and a display device, the cover panel including a heat sink layer; an impact absorbing layer on the heat sink layer; and an elastic pattern on at least one side of the impact absorbing layer.

Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.

Abstract: Methods, systems, apparatuses, and devices are described for transmitting a measurement report during wireless communications. When, for example, a low-power period (e.g., CDRX OFF period) is scheduled to begin during a time defined by a measurement event timer (TTT timer), a UE may modify the low-power period. The low-power period may be modified based, at least in part on determining the low-power period of the UE will begin during a time defined by a measurement event timer, a duration of the measurement event timer, and a duration of the low-power period. Modifying the low-power period may include delaying the start of the low-power state until after transmission of the MR associated with the measurement event timer or skipping the low-power period altogether. The UE may transmit the MR based, at least in part, on the modification.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure comprising a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer may include: a first under layer including a silicon-based alloy; a second under layer including a metal; and a blocking layer interposed between the first under layer and the second under layer and including an amorphous material.

Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.

Abstract: Provided are payment processing methods, payment processing servers, and/or computer programs for performing the payment processing methods, in which payment is made, without having to be directly connected to a buyer, according to the payment request received from a seller terminal of a seller. The payment request may be generated by combining a payment identification (ID) issued to a buyer terminal and sale information generated by the seller terminal. Further, communication may be initiated or performed based on transaction data without having to exchange personal ID information between the buyer and the seller.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an interface enhancement layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface enhancement layer may include an Fe-rich first layer; a Co-rich second layer formed over the first layer; and a metal layer formed over the second layer.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.

Abstract: According to one embodiment, a magnetoresistive memory device includes an electrode, a first layer which is provided on the electrode and includes an amorphous portion in at least a part of an electrode side, and a magnetoresisive element provided on the first layer.

Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.