Patents by Inventor Woo-Geun Lee

Woo-Geun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11032722
    Abstract: A scheduling method of giving a chance for transmission to a plurality of terminals in the same time period, and a device therefor are provided. The scheduling method includes: transmitting first scheduling information to terminals in a network, the first scheduling information defining transmitting/receiving terminals and a transmission time period; receiving channel measurement information including inter-terminal interference information from the terminals in the network; and generating second scheduling information defining transmission time periods and a plurality of transmitting/receiving terminals that do not interfere with each other by using the channel measurement information.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 8, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Geun Jin, Jin Kyeong Kim, Woo Yong Lee, Hyun Kyu Chung
  • Publication number: 20210143187
    Abstract: A substrate including a gate line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer, the third electrode spaced apart from the second electrode, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 13, 2021
    Inventors: Young-Wook LEE, Woo-Geun LEE, Ki-Won KIM, Hyun-Jung LEE, Ji-Soo OH
  • Publication number: 20210091163
    Abstract: A display device includes a substrate, a first conductive layer on the substrate, the first conductive layer including a data signal line, a first insulating layer on the first conductive layer, a semiconductor layer on the first insulating layer, the semiconductor layer including a first semiconductor pattern, a second insulating layer on the semiconductor layer, and a second conductive layer on the second insulating layer, the second conductive layer including a gate electrode disposed to overlap the first semiconductor pattern, a transistor first electrode disposed to overlap a part of the first semiconductor pattern, wherein the transistor first electrode is electrically connected to the data signal line through a contact hole that penetrates the first and second insulating layers, and a transistor second electrode disposed to overlap another part of the first semiconductor pattern.
    Type: Application
    Filed: June 4, 2020
    Publication date: March 25, 2021
    Applicant: Samsung Display Co., LTD.
    Inventors: Seung Sok SON, Woo Geun LEE, Seul Ki KIM, Kap Soo YOON, Hyun Woong BAEK, Jae Hyun LEE, Su Jung JUNG, Jung Kyoung CHO, Seung Ha CHOI, June Whan CHOI
  • Publication number: 20210036076
    Abstract: A display device includes a substrate having a display area and a pad area. A gate conductive layer disposed on the substrate includes a gate conductive metal layer and a gate capping layer. The gate conductive layer forms a gate electrode in the display area and a wire pad in the pad area that is exposed by a pad opening. An interlayer insulating film disposed on the gate conductive layer covers the gate electrode. A data conductive layer disposed on the interlayer insulating film in the display area includes source and drain electrodes. A passivation layer disposed on the data conductive layer covers the source and drain electrodes. A via layer is disposed on the passivation layer. A pixel electrode is disposed on the via layer. The pixel electrode is connected to the source electrode through a contact hole penetrating the via layer and the passivation layer.
    Type: Application
    Filed: June 8, 2020
    Publication date: February 4, 2021
    Inventors: Seul Ki KIM, Seung Sok SON, Kap Soo YOON, Woo Geun LEE, Su Jung JUNG, Seung Ha CHOI
  • Patent number: 10896920
    Abstract: A substrate including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a source electrode electrically connected to the oxide semiconductor layer pattern, a drain electrode electrically connected to the oxide semiconductor layer, the drain electrode spaced apart from the source electrode, and an insulating pattern including a first portion, which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: January 19, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young-Wook Lee, Woo-Geun Lee, Ki-Won Kim, Hyun-Jung Lee, Ji-Soo Oh
  • Publication number: 20200394978
    Abstract: A gate driver for a display device includes: a clock signal line to transfer a clock signal; and a plurality of stages to sequentially output a gate signal based upon the clock signal in response to a carry signal. The plurality of stages include a plurality of thin film transistors, and at least one of the plurality of thin film transistors includes a thin film transistor including an oxide semiconductor. The at least one thin film transistor includes a first gate electrode and a second gate electrode disposed in different layers, the oxide semiconductor is disposed between the first gate electrode and the second gate electrode, and the first gate electrode and the second gate electrode are connected to receive a common voltage signal.
    Type: Application
    Filed: March 4, 2020
    Publication date: December 17, 2020
    Inventors: Sung Hoon LIM, Kang Nam KIM, Seok Hwan BANG, Sung Hwan WON, Woo Geun LEE, Kyu Sik CHO, Soo Jung CHAE
  • Publication number: 20200372851
    Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 26, 2020
    Inventors: Kang Nam KIM, Sung Hoon LIM, Woo Geun LEE, Kyu Sik CHO, Jae Beom CHOI
  • Publication number: 20200358040
    Abstract: A method of manufacturing a thin film transistor includes: forming an active pattern on a substrate; forming an insulating layer and a gate electrode layer on the active pattern in order; forming a photoresist pattern on the gate electrode layer; forming a preliminary gate electrode by wet etching the gate electrode layer using the photoresist pattern; forming an insulating pattern by dry etching the insulating layer using the photoresist pattern and the preliminary gate electrode; and forming a gate electrode by wet etching a side surface of the preliminary gate electrode using the photoresist pattern.
    Type: Application
    Filed: March 27, 2020
    Publication date: November 12, 2020
    Inventors: Keum Hee LEE, Joongeol KIM, Kap Soo YOON, Woo Geun LEE, Seung-Ha CHOI, Jiyun HONG
  • Publication number: 20190355752
    Abstract: A substrate including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a source electrode electrically connected to the oxide semiconductor layer pattern, a drain electrode electrically connected to the oxide semiconductor layer, the drain electrode spaced apart from the source electrode, and an insulating pattern including a first portion, which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.
    Type: Application
    Filed: June 11, 2019
    Publication date: November 21, 2019
    Inventors: Young-Wook LEE, Woo-Geun LEE, Ki-Won KIM, Hyun-Jung LEE, Ji-Soo OH
  • Patent number: 10355025
    Abstract: A substrate including gate wirings including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate wirings and the oxide semiconductor layer pattern, data wirings including a data line crossing the gate line, a source electrode connected to one side of the oxide semiconductor layer pattern, and a drain electrode connected to another side of the oxide semiconductor layer, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young-Wook Lee, Woo-Geun Lee, Ki-Won Kim, Hyun-Jung Lee, Ji-Soo Oh
  • Patent number: 9954006
    Abstract: A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Je-Hun Lee, Ki-Won Kim, Do-Hyun Kim, Woo-Geun Lee, Kap-Soo Yoon
  • Publication number: 20180083040
    Abstract: A substrate including gate wirings including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate wirings and the oxide semiconductor layer pattern, data wirings including a data line crossing the gate line, a source electrode connected to one side of the oxide semiconductor layer pattern, and a drain electrode connected to another side of the oxide semiconductor layer, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 22, 2018
    Inventors: Young-Wook LEE, Woo-Geun LEE, Ki-Won KIM, Hyun-Jung LEE, Ji-Soo OH
  • Patent number: 9893203
    Abstract: One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: February 13, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seok Hwan Bang, Sook-Hwan Ban, Hyung Jun Kim, Woo Geun Lee, Hyeon Jun Lee
  • Patent number: 9825065
    Abstract: A substrate including gate wirings including gate line and a gate electrode disposed on the substrate, a storage line disposed on the same layer as the gate wirings, a gate insulating layer disposed on the gate wirings and the storage line, an oxide semiconductor layer pattern disposed on the gate insulating layer, data wirings including a data line crossing the gate line, a source electrode disposed on one side of the oxide semiconductor layer pattern, and a drain electrode disposed on another side of the oxide semiconductor layer, and an etch stopper including a first etch stopper portion disposed between the storage line and the data line and partially overlapping both the data line and the storage line.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: November 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young-Wook Lee, Woo-Geun Lee, Ki-Won Kim, Hyun-Jung Lee, Ji-Soo Oh
  • Patent number: 9647136
    Abstract: A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: May 9, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyun-Jung Lee, Sung-Haeng Cho, Woo-Geun Lee, Jang-Hoon Ha, Hee-Jun Byeon, Ji-Yun Hong, Ji-Soo Oh
  • Publication number: 20170110591
    Abstract: One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.
    Type: Application
    Filed: August 24, 2016
    Publication date: April 20, 2017
    Inventors: Seok Hwan BANG, Sook-Hwan BAN, Hyung Jun KIM, Woo Geun LEE, Hyeon Jun LEE
  • Publication number: 20170077144
    Abstract: A substrate including gate wirings including gate line and a gate electrode disposed on the substrate, a storage line disposed on the same layer as the gate wirings, a gate insulating layer disposed on the gate wirings and the storage line, an oxide semiconductor layer pattern disposed on the gate insulating layer, data wirings including a data line crossing the gate line, a source electrode disposed on one side of the oxide semiconductor layer pattern, and a drain electrode disposed on another side of the oxide semiconductor layer, and an etch stopper including a first etch stopper portion disposed between the storage line and the data line and partially overlapping both the data line and the storage line.
    Type: Application
    Filed: November 3, 2016
    Publication date: March 16, 2017
    Inventors: Young-Wook LEE, Woo-Geun LEE, Ki-Won KIM, Hyun-Jung LEE, Ji-Soo OH
  • Publication number: 20170077246
    Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
    Type: Application
    Filed: November 4, 2016
    Publication date: March 16, 2017
    Inventors: Pil-Sang YUN, Ki-Won KIM, Hye-Young RYU, Woo-Geun LEE, Seung-Ha CHOI, Jae-Hyoung YOUN, Kyoung-Jae CHUNG, Young-Wook LEE, Je-Hun LEE, Kap-Soo YOON, Do-Hyun KIM, Dong-Ju YANG, Young-Joo CHOI
  • Publication number: 20170040349
    Abstract: A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 9, 2017
    Inventors: Je-Hun LEE, Ki-Won KIM, Do-Hyun KIM, Woo-Geun LEE, Kap-Soo YOON
  • Patent number: 9524992
    Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: December 20, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hye Young Ryu, Hee Jun Byeon, Woo Geun Lee, Kap Soo Yoon, Yoon Ho Kim, Chun Won Byun