Patents by Inventor Woo-Geun Lee

Woo-Geun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120228604
    Abstract: A thin film transistor array panel includes a gate electrode on an insulating substrate, a gate insulating layer on the gate electrode, a semiconductor on the gate insulating layer, a thin film transistor including a source electrode and a drain electrode on the oxide semiconductor, and a pixel electrode which is connected to the drain electrode. The semiconductor includes a first layer having a relatively low fluorine content and a second layer having a relatively high fluorine content. The second layer of the semiconductor is only between the first layer of the semiconductor and the source electrode, and between the first layer of the semiconductor and the drain electrode.
    Type: Application
    Filed: February 21, 2012
    Publication date: September 13, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Ha CHOI, Sung Haeng CHO, Woo Geun LEE, Kap Soo YOON, Sho Yeon KIM
  • Publication number: 20120217493
    Abstract: A thin film transistor array panel includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a first electrode and an oxide semiconductor disposed directly on the gate insulating layer; a source electrode and a drain electrode formed on the oxide semiconductor; a passivation layer disposed on the first electrode, the source electrode, and the drain electrode; and a second electrode disposed on the passivation layer.
    Type: Application
    Filed: February 3, 2012
    Publication date: August 30, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Won LEE, Woo Geun LEE, Kap Soo YOON, Ki-Won KIM, Hyun-Jung LEE, Hee-Jun BYEON, Ji-Soo OH
  • Publication number: 20120211753
    Abstract: In a display substrate and a method of manufacturing the display substrate, the display substrate includes a data line, a channel pattern, an insulating pattern and a pixel electrode. The data line extends in a direction on a base substrate. The channel pattern is disposed in a separate region between an input electrode connected to the data line and an output electrode spaced apart from the input electrode. The channel pattern makes contact with the input electrode and the output electrode on the input and output electrodes. The insulating pattern is spaced apart from the channel pattern on the base substrate and includes a contact hole exposing the output electrode. The pixel electrode is formed on the insulating pattern to make contact with the output electrode through the contact hole. Thus, a damage of the oxide semiconductor layer may be minimized and a manufacturing process may be simplified.
    Type: Application
    Filed: December 16, 2011
    Publication date: August 23, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Won KIM, Je-Hun LEE, Sung-Haeng CHO, Woo-Geun LEE, Kap-Soo YOON, Do-Hyun KIM, Seung-Ha CHOI
  • Publication number: 20120194414
    Abstract: A liquid crystal display to prevent light leakage with an improvement of aperture ratio and a reduction of load of a data line is provided. The liquid crystal display includes a gate line and a storage electrode line formed on a insulating substrate and apart from each other, a first data line and a second data line intersecting the gate line, a first pixel electrode defined by the gate line and the first data line, and a second pixel electrode defined by the gate line and the second data line and neighboring the first pixel electrode. Also, a blocking electrode between the first pixel electrode and the second pixel electrode is included, wherein at least portion of the first data line is disposed under the first pixel electrode, and at least portion of the blocking electrode is disposed under the second pixel electrode and apart from the first data line.
    Type: Application
    Filed: March 13, 2012
    Publication date: August 2, 2012
    Inventors: Woo-Geun LEE, Shi-Yul Kim, Jae-Hyoung Youn, Young-Wook Lee
  • Publication number: 20120193634
    Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.
    Type: Application
    Filed: April 11, 2012
    Publication date: August 2, 2012
    Inventors: Young-Wook Lee, Hong-Suk Yoo, Jean-Ho Song, Jae-Hyoung Youn, Woo-Geun Lee, Ki-Won Kim, Jong-In Kim
  • Patent number: 8216865
    Abstract: A display device includes a gate pattern, a semiconductor pattern, a source pattern and a pixel electrode are provided. The gate pattern is formed on a base substrate and includes a gate line and a gate electrode. The semiconductor pattern is formed on the base substrate having the gate pattern and includes an oxide semiconductor. The source pattern is formed from a data metal layer and formed on the base substrate having the semiconductor pattern, and includes a data line, a source electrode and a drain electrode. The data metal layer includes a first copper alloy layer, and a lower surface of the data metal layer substantially coincides with an upper surface of the semiconductor pattern. The pixel electrode is formed on the base substrate having the source pattern and electrically connected to the drain electrode. Thus, manufacturing processes may be simplified, and reliability may be improved.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: July 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Joo Choi, Woo-Geun Lee, Hye-Young Ryu, Ki-Won Kim
  • Patent number: 8203662
    Abstract: Provided is a thin-film transistor (TFT) substrate. The TFT substrate includes: an insulating substrate; a semiconductor pattern which is formed on the insulating substrate, the semiconductor pattern having a top surface and a bottom surface; a source electrode and a drain electrode which are disposed on the top and bottom surfaces of the semiconductor pattern, respectively; a gate electrode which is disposed alongside the semiconductor pattern with a gate insulating film interposed therebetween; a data line which is connected to the source electrode and extends in a first direction; a gate line which is connected to the gate electrode and extends in a second direction; and a pixel electrode which is connected to the drain electrode and is formed in a pixel region.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: June 19, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoon Kang, Yun-Seok Lee, Jae-Sung Kim, Yang-Ho Jung, Young-Je Cho, Cheon-Jae Maeng, Woo-Geun Lee
  • Publication number: 20120146029
    Abstract: A thin film transistor array panel includes an insulating substrate, a gate line disposed on the insulating substrate having a gate electrode, a first gate insulating layer disposed on the gate line and made of silicon nitride, a second gate insulating layer disposed on the first gate insulating layer and made of silicon oxide, an oxide semiconductor disposed on the second gate insulating layer, a data line disposed on the oxide semiconductor and having a source electrode, a drain electrode disposed on the oxide semiconductor and facing the source electrode, and a pixel electrode that is connected to the drain electrode. A thickness of the second gate insulating layer may range from 200 ? to less than 500 ?.
    Type: Application
    Filed: July 18, 2011
    Publication date: June 14, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Joo CHOI, Woo Geun LEE, Kap Soo YOON, Ki-Won KIM, Sang Wan JIN, Jae Won SONG, Zhu Xun
  • Publication number: 20120113346
    Abstract: Provided are a display substrate, a display device, and a method of manufacturing the display substrate. The display substrate includes: a substrate in which a pixel region is defined; a gate electrode and a gate pad are formed on the substrate; a gate insulating layer formed on the gate electrode and the gate pad; a buffer layer pattern overlaps the gate electrode and is formed on the gate insulating layer; an insulating film pattern formed on the buffer layer pattern; an oxide semiconductor pattern formed on the insulating film pattern; a source electrode formed on the oxide semiconductor pattern; and a drain electrode formed on the oxide semiconductor pattern and is separated from the source electrode.
    Type: Application
    Filed: October 19, 2011
    Publication date: May 10, 2012
    Inventors: Seung-Ha CHOI, Kyoung-Jae Chung, Woo-Geun Lee
  • Patent number: 8173493
    Abstract: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: May 8, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Gab Kim, Woo-Geun Lee, Shi-Yul Kim, Jin-Ho Ju, Jang-Soo Kim, Sang-Woo Whangbo, Min-Seok Oh, Hye-Young Ryu, Hong-Kee Chin
  • Patent number: 8174020
    Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: May 8, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Wook Lee, Hong-Suk Yoo, Jean-Ho Song, Jae-Hyoung Youn, Woo-Geun Lee, Ki-Won Kim, Jong-In Kim
  • Publication number: 20120104384
    Abstract: A thin-film transistor (TFT) includes a gate electrode, an oxide semiconductor pattern, a source electrode, a drain electrode and an etch stopper. The gate electrode is formed on a substrate. The oxide semiconductor pattern is disposed in an area overlapping with the gate electrode. The source electrode is partially disposed on the oxide semiconductor pattern. The drain electrode is spaced apart from the source electrode, faces the source electrode, and is partially disposed on the oxide semiconductor pattern. The etch stopper has first and second end portions. The first end portion is disposed between the oxide semiconductor pattern and the source electrode, and the second end portion is disposed between the oxide semiconductor pattern and the drain electrode. A sum of first and second overlapping length is between about 30% and about 99% of a total length of the etch stopper.
    Type: Application
    Filed: July 28, 2011
    Publication date: May 3, 2012
    Inventors: Young-Joo CHOI, Jae-Won SONG, Xun ZHU, Sang-Wan JIN, Woo-Geun LEE
  • Patent number: 8144280
    Abstract: A liquid crystal display to prevent light leakage with an improvement of aperture ratio and a reduction of load of a data line is provided. The liquid crystal display includes a gate line and a storage electrode line formed on a insulating substrate and apart from each other, a first data line and a second data line intersecting the gate line, a first pixel electrode defined by the gate line and the first data line, and a second pixel electrode defined by the gate line and the second data line and neighboring the first pixel electrode. Also, a blocking electrode between the first pixel electrode and the second pixel electrode is included, wherein at least portion of the first data line is disposed under the first pixel electrode, and at least portion of the blocking electrode is disposed under the second pixel electrode and apart from the first data line.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Geun Lee, Shi-Yul Kim, Jae-Hyoung Youn, Young-Wook Lee
  • Publication number: 20120037906
    Abstract: A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.
    Type: Application
    Filed: May 24, 2011
    Publication date: February 16, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hye-Young RYU, Woo-Geun LEE, Young-Joo CHOI, Kyoung-Jae CHUNG, Jin-Won LEE, Seung-Ha CHOI, Hee-Jun BYEON, Pil-Sang YUN
  • Publication number: 20120037910
    Abstract: A display substrate includes; a gate pattern including a gate electrode disposed on a substrate, a gate insulation layer disposed on the substrate and the gate pattern, an insulation pattern including; a first thickness part disposed on a first area of the gate insulation layer overlapping the gate electrode and a second thickness part disposed on a second area of the gate insulation layer adjacent to the first area, an oxide semiconductor pattern disposed on the first thickness part of the first area, an etch stopper disposed on the oxide semiconductor pattern, a source pattern including a source electrode and a drain electrode which contact the oxide semiconductor pattern, and a pixel electrode which contacts the drain electrode.
    Type: Application
    Filed: May 19, 2011
    Publication date: February 16, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Joo CHOI, Woo-Geun LEE, Do-Hyun KIM
  • Publication number: 20120018720
    Abstract: A display substrate includes a gate line extending in a first direction on a base substrate, a data line on the base substrate and extending in a second direction crossing the first direction, a gate insulating layer on the gate line, a thin-film transistor and a pixel electrode. The thin-film transistor includes a gate electrode electrically connected the gate line, an oxide semiconductor pattern, and source and drain electrodes on the oxide semiconductor pattern and spaced apart from each other. The oxide semiconductor pattern includes a first semiconductor pattern including indium oxide and a second semiconductor pattern including indium-free oxide. The pixel electrode is electrically connected the drain electrode.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 26, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Woo PARK, Dong-Hoon LEE, Sung-Haeng CHO, Woo-Geun LEE, Hye-Young RYU, Young-Joo CHOI
  • Patent number: 8077275
    Abstract: A display substrate includes a transistor layer, a plurality of color filters, a first blocking member, a supporting member, a circuit part, a second blocking member and a protruding member. The first blocking member is disposed between different color filters. The supporting member maintains a distance between a base substrate and a substrate facing the base substrate. A circuit part is disposed in a peripheral area surrounding a display area, and the circuit part includes a metal pattern and a contact electrode in contact with the metal pattern. The second blocking member includes substantially the same material as the first blocking member and the second blocking member covers the circuit part. The protruding member includes substantially the same material as the second blocking member, and is integrally formed with the second blocking member.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: December 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Duk Yang, Jang-Soo Kim, Woo-Geun Lee, Ki-Won Kim, Sang-Ki Kwak, Hyang-Shik Kong, Sang-Hun Lee
  • Publication number: 20110297930
    Abstract: A TFT display panel having a high charge mobility and making it possible to obtain uniform electric characteristics with respect to a large-area display is provided as well as a manufacturing method thereof. A TFT display panel includes a gate electrode formed on an insulation substrate, a first gate insulting layer formed of SiNx on the gate electrode, a second gate insulting layer formed of SiOx on the first gate insulting layer, an oxide semiconductor layer formed to overlap the gate electrode and having a channel part, and a passivation layer formed of SiOx on the oxide semiconductor layer and the gate electrode, and the passivation layer includes a contact hole exposing the drain electrode. The contact hole has a shape in which the passivation layer of a portion directly exposed together with a metal occupies an area smaller than the upper passivation layer.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 8, 2011
    Inventors: Seung-Ha CHOI, Kyoung-Jae Chung, Woo-Geun Lee
  • Publication number: 20110284852
    Abstract: A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.
    Type: Application
    Filed: March 16, 2011
    Publication date: November 24, 2011
    Inventors: Ki-Won KIM, Kap-Soo Yoon, Woo-Geun Lee, Yeong-Keun Kwon, Hye-Young Ryu, Jin-Won Lee, Hyun-Jung Lee
  • Patent number: 8058114
    Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: November 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Soo Kim, Hong-Long Ning, Bong-Kyun Kim, Hong-Sick Park, Shi-Yul Kim, Chang-Oh Jeong, Sang-Gab Kim, Jae-Hyoung Youn, Woo-Geun Lee, Yang-Ho Bae, Pil-Sang Yun, Jong-Hyun Choung, Sun-Young Hong, Ki-Won Kim, Byeong-Jin Lee, Young-Wook Lee, Jong-In Kim, Byeong-Beom Kim, Nam-Seok Suh