Abstract: Memory systems and memory dies are provided. The memory system of the present disclosure includes a plurality of memory dies stacked within the memory system. Each memory die includes a numbering circuit configured to generate an output number signal according to an input number signal. The numbering circuit includes a plurality of calculating circuits coupled in series. A current stage calculating circuit is configured to receive a first output bit from a previous stage calculating circuit and a corresponding bit of the input number signal to generate the first output bit and a second output bit as a correspond bit of the output number signal.

Abstract: A semiconductor device structure includes a first gate structure extending along a first direction and electrically connected to a first transistor, a second gate structure extending along the first direction and electrically connected to a second transistor, a first active region extending along a second direction different from the first direction and across the first gate structure and the second gate structure, and a first conductive element extending along the second direction and disposed on the first active region. The first conductive element is electrically connected to the first active region. The first conductive element is electrically connected to the first active region, such that a short circuit between the first active region and the third transistor is formed. The first gate structure and the first active region form a first fuse element, and the second gate structure and the first active region form a second fuse element.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh one of a plurality of word lines during a first refresh cycle in response to a refresh signal, a random number generator configured to generate a first number, a counter configured to receive the first number as an initial value of the counter, wherein the counter is configured to be turned on in response to the refresh signal, and an address register configured to store an address of a first word line active when the counter decrements to zero. The controller is configured to obtain the address of the first word line and protect a second word line during a second refresh cycle, wherein an address of the second word line is adjacent to the address of the first word line.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes: a random number generator, a counter, and a controller. The random number generator includes a first logic gate and a second logic gate configured to generate a first output and a second output, respectively, according to the address of the first word line and the address of the first accessed word line. The random number generator further includes a switch configured to select one of the first output and the second output to be a first number. The counter is configured to receive the first number and count down from the first number. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh adjacent word lines of the second accessed word line during a second refresh cycle.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes: a random number generator, a counter, and a controller. The random number generator includes a first logic gate and a second logic gate configured to generate a first output and a second output, respectively, according to the address of the first word line and the address of the first accessed word line. The random number generator further includes a switch configured to select one of the first output and the second output to be a first number. The counter is configured to receive the first number and count down from the first number. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh adjacent word lines of the second accessed word line during a second refresh cycle.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes: a random number generator, a counter, and a controller. The random number generator includes a first logic gate and a second logic gate configured to generate a first output and a second output, respectively, according to the address of the first word line and the address of the first accessed word line. The random number generator further includes a switch configured to select one of the first output and the second output to be a first number. The counter is configured to receive the first number and count down from the first number. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh adjacent word lines of the second accessed word line during a second refresh cycle.

Abstract: A method for adaptive noise suppression on data strobe signals is provided. The method includes the following steps: determining whether a first data strobe signal and a second data strobe signal satisfy a first condition; in response to the first data strobe signal and the second data strobe signal satisfying the first condition, determining whether a mode register setting value (MRSV) associated with a first on-die terminator and a second on-die terminator is greater than N; and in response to the MRSV being not greater than N, decoupling a first resistor and a second resistor from a first input terminal and a second input terminal of a differential amplifier, respectively; and in response to the MRSV being greater than N, coupling the first resistor and the second resistor to the first input terminal and the second input terminal of the differential amplifier, respectively.

Abstract: A method for adaptive noise suppression on data strobe signals is provided. The method includes the following steps: determining whether a first data strobe signal and a second data strobe signal satisfy a first condition; in response to the first data strobe signal and the second data strobe signal satisfying the first condition, determining whether a mode register setting value (MRSV) associated with a first on-die terminator and a second on-die terminator is greater than N; and in response to the MRSV being not greater than N, decoupling a first resistor and a second resistor from a first input terminal and a second input terminal of a differential amplifier, respectively; and in response to the MRSV being greater than N, coupling the first resistor and the second resistor to the first input terminal and the second input terminal of the differential amplifier, respectively.

Abstract: A method for adaptive noise suppression on data strobe signals is provided. The method includes the following steps: determining whether a first data strobe signal and a second data strobe signal satisfy a first condition; in response to the first data strobe signal and the second data strobe signal satisfying the first condition, determining whether a mode register setting value (MRSV) associated with a first on-die terminator and a second on-die terminator is greater than N; and in response to the MRSV being not greater than N, decoupling a first resistor and a second resistor from a first input terminal and a second input terminal of a differential amplifier, respectively; and in response to the MRSV being greater than N, coupling the first resistor and the second resistor to the first input terminal and the second input terminal of the differential amplifier, respectively.

Abstract: A method for controlling data strobe signals for use in a memory device is provided. The memory device includes a receiver circuit having a differential amplifier, an auxiliary control circuit, and a data strobe control circuit. The method includes the following steps: utilizing the differential amplifier to amplify a first data strobe signal and a second data strobe signal received from a memory controller to generate a third data strobe signal and a fourth data strobe signal; utilizing the auxiliary control circuit to generate a disable control signal using the first data strobe signal and the second data strobe signal; and disabling the data strobe control circuit in response to the disable control signal being in a high logic state.

Abstract: A bonding pad structure and a method of manufacturing a bonding pad structure are provided. The bonding pad structure includes a carrier, a first conductive layer disposed over the carrier, a second conductive layer disposed on the first conductive layer and contacting the first conductive layer, and a third conductive layer disposed on the second conductive layer and contacting the second conductive layer. The bonding pad structure also includes a first passivation layer disposed on the first conductive layer and contacting at least one of the first conductive layer or the second conductive layer. An upper surface of the third conductive layer facing away from the carrier is exposed from the first passivation layer.

Abstract: A method for controlling data strobe signals for use in a memory device is provided. The memory device includes a receiver circuit having a differential amplifier, an auxiliary control circuit, and a data strobe control circuit. The method includes the following steps: utilizing the differential amplifier to amplify a first data strobe signal and a second data strobe signal received from a memory controller to generate a third data strobe signal and a fourth data strobe signal; utilizing the auxiliary control circuit to generate a disable control signal using the first data strobe signal and the second data strobe signal; and disabling the data strobe control circuit in response to the disable control signal being in a high logic state.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh one of word lines during a first refresh cycle in response to a refresh signal, a number trimmer configured to generate a modified first number according to a first number generated by a random number generator, wherein the modified first number is less than a first predetermined number. The memory device further includes a counter configured to receive the modified first number as an initial value, and to be turned on in response to the refresh signal. The controller is configured to obtain an address of a first word line being accessed when the counter counts to zero, and refresh a second word line during a second refresh cycle, wherein an address of the second word line is adjacent to the address of the first word line.

Abstract: A WBGA package and a method of manufacturing a WBGA package are provided. The WBGA package includes a first substrate having a first through hole and a second substrate having a second through hole over the first through hole of the first substrate. The WBGA package also includes an electronic component having an active surface over the second through hole of the second substrate.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a first electronic component, a second electronic component, a bonding wire, and an encapsulant. The substrate has a lower surface and an upper surface opposite to the lower surface. The first electronic component is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic component and the substrate and extends within the substrate. The second electronic component is disposed on the upper surface of the substrate. The second electronic component has an active surface facing the substrate. The encapsulant is disposed on the upper surface of the substrate. The encapsulant extends within the substrate and encapsulates the bonding wire.

Abstract: A memory device and a noise suppression method thereof are provided. An input receiving circuit of a memory circuit receives a data strobe differential signal pair. A noise suppression circuit provides a noise suppression resistor connected between an input terminal of the input receiving circuit and a ground voltage during a write data strobe signal off period before a write preamble period.

Abstract: A WBGA package and a method of manufacturing a WBGA package are provided. The WBGA package includes a first substrate having a first through hole and a second substrate having a second through hole over the first through hole of the first substrate. The WBGA package also includes an electronic component having an active surface over the second through hole of the second substrate.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh a first word line and a first protected word line during a first refresh cycle in response to a refresh signal, a random number generator configured to receive an address of the first word line and an address of the first protected word line to generate a first number, a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value of the counter, and configured to be turned on in response to the refresh signal. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh a second protected word line, adjacent to the second accessed word line, during a second refresh cycle.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh a first word line and a first protected word line during a first refresh cycle in response to a refresh signal, a random number generator configured to receive an address of the first word line and an address of the first protected word line to generate a first number, a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value of the counter, and configured to be turned on in response to the refresh signal. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh a second protected word line, adjacent to the second accessed word line, during a second refresh cycle.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes providing a substrate having a lower surface and an upper surface opposite to the lower surface; forming an opening extending between the upper surface and the lower surface of the substrate; attaching a first electronic component to the upper surface of the substrate, wherein an active surface of the first electronic component faces the upper surface of the substrate; attaching a second electronic component to the first electronic component, wherein an active surface of the second electronic component faces the upper surface of the substrate; and forming a bonding wire on the substrate, wherein the bonding wire passes through the opening of the substrate and electrically connects the substrate and one of the first electronic component or the second electronic component.