Abstract: A memory device is provided, which includes a memory cell array, a control circuit, and an interface circuit. The interface circuit includes a receiver circuit configured to amplify a first data strobe signal and a second data strobe signal received from a memory controller to generate a third data strobe signal and a fourth data strobe signal. In response to a first logic state of the first data strobe signal and a second logic state the second data strobe signal satisfying a predetermined condition, the receiver circuit adjusts a third logic state of the third data strobe signal and/or a fourth logic state of the fourth data strobe signal. The control circuit performs a write operation on the memory cell array according to the write command, the third data strobe signal, and the fourth data strobe signal.

Abstract: A memory device is provided, which includes a memory cell array, a control circuit, and an interface circuit. The interface circuit includes a receiver circuit configured to amplify a first data strobe signal and a second data strobe signal received from a memory controller to generate a third data strobe signal and a fourth data strobe signal. In response to a first logic state of the first data strobe signal and a second logic state the second data strobe signal satisfying a predetermined condition, the receiver circuit adjusts a third logic state of the third data strobe signal and/or a fourth logic state of the fourth data strobe signal. The control circuit performs a write operation on the memory cell array according to the write command, the third data strobe signal, and the fourth data strobe signal.

Abstract: A control unit in a memory and a method of controlling a memory are provided. The control unit includes a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage is configured to receive a first signal and a second signal. The second input stage is configured to receive the first signal and the second signal. The first output stage is connected to the first input stage and configured to generate a first processed signal. The second output stage is connected to the second input stage and configured to generate a second processed signal. If the first signal and the second signal are identical, the first processed signal and the second processed signal are different.

Abstract: A memory system includes a controller and a memory circuit. Controller outputs a first data strobe signal and a second data strobe signal. Memory circuit is coupled to controller, and is configured to receive first data strobe signal and second data strobe signal. Memory circuit includes a receiver. Receiver includes a logic conversion circuit. Logic conversion circuit is coupled to controller. When first and second data strobe signal are at the same voltage level, logic conversion circuit is configured to convert first second data strobe signals into third and fourth data strobe signals. Third data strobe signal and fourth data strobe signal converted by logic conversion circuit are at different voltage levels. When first and second data strobe signals are at different voltage levels, logic conversion circuit is configured to pass first and second data strobe signal and as third and fourth data strobe signals.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate. The method also includes attaching an electronic component to the substrate. The method further includes attaching a fixing feature to an upper surface of the electronic component. In addition, the method includes forming a bonding wire connecting the substrate and the electronic component. The bonding wire is at least partially disposed on the fixing feature.

Abstract: A control unit in a memory and a method of controlling a memory are provided. The control unit includes a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage is configured to receive a first signal and a second signal. The second input stage is configured to receive the first signal and the second signal. The first output stage is connected to the first input stage and configured to generate a first processed signal. The second output stage is connected to the second input stage and configured to generate a second processed signal. If the first signal and the second signal are identical, the first processed signal and the second processed signal are different.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure, a second gate structure, and a first active region. The first gate structure extends along a first direction and is electrically connected to a first transistor. The second gate structure extends along the first direction and is electrically connected to a second transistor. The first active region extends along a second direction different from the first direction and across the first gate structure and the second gate structure. The first gate structure and the first active region collaboratively form a first fuse element. The second gate structure and the first active region collaboratively form a second fuse element.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh one of word lines during a first refresh cycle in response to a refresh signal, a number trimmer configured to generate a modified first number according to a first number generated by a random number generator, wherein the modified first number is less than a first predetermined number. The memory device further includes a counter configured to receive the modified first number as an initial value, and to be turned on in response to the refresh signal. The controller is configured to obtain an address of a first word line being accessed when the counter counts to zero, and refresh a second word line during a second refresh cycle, wherein an address of the second word line is adjacent to the address of the first word line.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh one of word lines during a first refresh cycle in response to a refresh signal, a number trimmer configured to generate a modified first number according to a first number generated by a random number generator, wherein the modified first number is less than a first predetermined number. The memory device further includes a counter configured to receive the modified first number as an initial value, and to be turned on in response to the refresh signal. The controller is configured to obtain an address of a first word line being accessed when the counter counts to zero, and refresh a second word line during a second refresh cycle, wherein an address of the second word line is adjacent to the address of the first word line.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes providing a substrate having a lower surface and an upper surface opposite to the lower surface; forming an opening extending between the upper surface and the lower surface of the substrate; attaching a first electronic component to the upper surface of the substrate, wherein an active surface of the first electronic component faces the upper surface of the substrate; attaching a second electronic component to the first electronic component, wherein an active surface of the second electronic component faces the upper surface of the substrate; and forming a bonding wire on the substrate, wherein the bonding wire passes through the opening of the substrate and electrically connects the substrate and one of the first electronic component or the second electronic component.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh one of a plurality of word lines during a first refresh cycle in response to a refresh signal, a random number generator configured to generate a first number, a counter configured to receive the first number as an initial value of the counter, wherein the counter is configured to be turned on in response to the refresh signal, and an address register configured to store an address of a first word line active when the counter decrements to zero. The controller is configured to obtain the address of the first word line and protect a second word line during a second refresh cycle, wherein an address of the second word line is adjacent to the address of the first word line.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh one of a plurality of word lines during a first refresh cycle in response to a refresh signal, a random number generator configured to generate a first number, a counter configured to receive the first number as an initial value of the counter, wherein the counter is configured to be turned on in response to the refresh signal, and an address register configured to store an address of a first word line active when the counter decrements to zero. The controller is configured to obtain the address of the first word line and protect a second word line during a second refresh cycle, wherein an address of the second word line is adjacent to the address of the first word line.

Abstract: A probing device includes a probe station having a platform with an opening; a manipulator on the platform and having a probe; a test head; and a socket disposed on the test head and configured to support a DUT. The test head has a moving part configured to allow the DUT to be moved with respect to the probe station.

Abstract: A method for determining a status of a fuse element are provided. The method includes providing the memory device including a first terminal and a second terminal; applying a first power signal on the first terminal of the semiconductor device, wherein the memory device includes a configurable reference resistor unit electrically coupled to the fuse element; obtaining an evaluation signal, in response to the first power signal, at the second terminal of the memory device; and identifying the evaluation signal to determine whether the memory device is redundant.

Abstract: A semiconductor device is provided, which includes a semiconductor die and a redistribution layer. The redistribution layer is formed on the semiconductor die, and includes a plurality of center pads, a plurality of edge pads, and a plurality of conductive wires electrically connecting the plurality of center pads to the plurality of edge pads. Each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle.

Abstract: A semiconductor device is provided, which includes a semiconductor die and a redistribution layer. The redistribution layer is formed on the semiconductor die, and includes a plurality of center pads, a plurality of edge pads, and a plurality of conductive wires electrically connecting the plurality of center pads to the plurality of edge pads. Each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle.

Abstract: A wafer structure includes a plurality of chips and a plurality of dummy connectors. The chips are separated from each other. Each of the chips includes a body and a plurality of conductive pads. The conductive pads are respectively and at least partially disposed on the body. The dummy connectors are connected with each other. Each of the dummy connectors is connected between adjacent two of the bodies. Each of the conductive pads is further at least partially disposed on a corresponding one of the dummy connectors.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure, a second gate structure, and a first active region. The first gate structure extends along a first direction and is electrically connected to a first transistor. The second gate structure extends along the first direction and is electrically connected to a second transistor. The first active region extends along a second direction different from the first direction and across the first gate structure and the second gate structure. The first gate structure and the first active region collaboratively form a first fuse element. The second gate structure and the first active region collaboratively form a second fuse element.

Abstract: A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.

Abstract: A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.