Abstract: The present application provides a method for preparing a semiconductor package The method includes bonding a bottom device die onto a package substrate; attaching a top device die onto the bottom device die; attaching an additional package substrate onto the top device die; establishing electrical connection between the additional package substrate and the top device die, between the additional package substrate and the package substrate, and between the top device die and the package substrate; and encapsulating the bottom device die, the top device die and the additional package substrate by an encapsulant.

Abstract: The present disclosure provides a method for determining status of a fuse element of a memory device. The method includes providing the memory device including a first terminal and a second terminal and applying a first power signal on the first terminal of the semiconductor device. The memory device includes a configurable reference resistor unit electrically coupled to the fuse element. The method also includes obtaining an evaluation signal at the second terminal of the memory device and identifying the evaluation signal to determine whether the memory device is redundant. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to turn on the first transistor.

Abstract: A semiconductor circuit and semiconductor device for determining status of a fuse element are provided. The semiconductor circuit includes a configurable reference resistor unit with a first terminal receiving a first power signal and a second terminal electrically coupled to the fuse element. The semiconductor circuit also includes a latch circuit for reading a first status signal of a first node between the configurable reference resistor unit and the fuse element. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to be provided to the gate of the first transistor.

Abstract: A method includes following operations: a delay line delaying a first clock signal by a delay time to generate an output signal; a controller delaying the output signal by a first time interval to generate a first signal; the controller delaying the first clock signal by a second time interval shorter than the first time interval to generate a second clock signal; and the controller controlling the delay line according to the first signal and the second clock signal to adjust the delay time. A delay locked loop device is also disclosed herein.

Abstract: A data receiving circuit is provided. The data receiving circuit includes a first transistor, a second transistor, a third transistor, and a latch circuit. The first transistor has a gate configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The second transistor has a gate configured to receive a first signal and a drain connected to the latch circuit. The third transistor has a gate configured to receive the first signal and a drain connected to the latch circuit. The second transistor and the third transistor are configured to provide a current to the latch circuit in response to the first signal.

Abstract: The disclosure provides an anti-fuse device including an anti-fuse unit and a sensing circuit. The anti-fuse unit includes a first anti-fuse and a second anti-fuse serially connected between a first terminal of the anti-fuse unit and a second terminal of the anti-fuse unit. The sensing circuit is coupled to the first terminal and the second terminal of the anti-fuse unit for sensing a blown state of the anti-fuse unit.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.

Abstract: A semiconductor circuit and semiconductor device for determining status of a fuse element are provided. The semiconductor circuit includes a configurable reference resistor unit with a first terminal receiving a first power signal and a second terminal electrically coupled to the fuse element. The semiconductor circuit also includes a latch circuit for reading a first status signal of a first node between the configurable reference resistor unit and the fuse element. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to be provided to the gate of the first transistor.

Abstract: The disclosure provides an anti-fuse device including an anti-fuse unit and a sensing circuit. The anti-fuse unit includes a first anti-fuse and a second anti-fuse serially connected between a first terminal of the anti-fuse unit and a second terminal of the anti-fuse unit. The sensing circuit is coupled to the first terminal and the second terminal of the anti-fuse unit for sensing a blown state of the anti-fuse unit.

Abstract: The present disclosure provides a method for determining status of a fuse element of a memory device. The method includes providing the memory device including a first terminal and a second terminal and applying a first power signal on the first terminal of the semiconductor device. The memory device includes a configurable reference resistor unit electrically coupled to the fuse element. The method also includes obtaining an evaluation signal at the second terminal of the memory device and identifying the evaluation signal to determine whether the memory device is redundant. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to turn on the first transistor.

Abstract: A chip-package device includes a substrate, a first chip, a first conductive layer, first wirings, and second wirings. The substrate includes a first top surface and first connection pads disposed on the first top surface. The first chip is disposed on the first top surface, and the first chip includes a second top surface and second connection pads disposed on the second top surface. The first conductive layer is disposed on the second top surface. The first wirings connect the first connection pads and the first conductive layer, and the second wirings connect the second connection pads and another side of the first conductive layer. Each of the first wirings and each of the second wirings respectively connect opposite sides of the first conductive layer.

Abstract: A delay lock loop circuit includes a receiver, a delay line circuit, a clock signal generator and a phase detecting circuit. The receiver receives a clock signal and a reference voltage and generates a reference clock signal according to the clock signal and the reference voltage. The delay line circuit is coupled to the receiver and generates a delayed clock signal by delaying the reference clock signal with a delay indication signal. The clock signal generator generates an output clock signal according to the delayed clock signal. The phase detecting circuit generates a detection result by sampling the reference clock signal with a feedback clock signal generated by the output clock signal, and generates the delay indication signal according to a digital value of the detection result.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure, a second gate structure, and a first active region. The first gate structure extends along a first direction and is electrically connected to a first transistor. The second gate structure extends along the first direction and is electrically connected to a second transistor. The first active region extends along a second direction different from the first direction and across the first gate structure and the second gate structure. The first gate structure and the first active region collaboratively form a first fuse element. The second gate structure and the first active region collaboratively form a second fuse element.

Abstract: A method for determining a status of a fuse element are provided. The method includes providing the memory device including a first terminal and a second terminal; applying a first power signal on the first terminal of the semiconductor device, wherein the memory device includes a configurable reference resistor unit electrically coupled to the fuse element; obtaining an evaluation signal, in response to the first power signal, at the second terminal of the memory device; and identifying the evaluation signal to determine whether the memory device is redundant.

Abstract: A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and a current source. The data input circuit is configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The current source is configured to provide a current to the latch circuit. The current source is different from the data input circuit.

Abstract: A semiconductor circuit and a semiconductor device for determining a status of a fuse element are provided. The semiconductor circuit includes a configurable reference resistor unit with a first terminal receiving a first power signal and a second terminal electrically coupled to the fuse element. The semiconductor circuit also includes a first switching circuit electrically connecting the configurable reference resistor unit and the fuse element and a latch circuit for reading an evaluation signal of a first node between the configurable reference resistor unit and the fuse element.

Abstract: A data receiving circuit is provided. The data receiving circuit includes a first transistor, a second transistor, a third transistor, and a latch circuit. The first transistor has a gate configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The second transistor has a gate configured to receive a first signal and a drain connected to the latch circuit. The third transistor has a gate configured to receive the first signal and a drain connected to the latch circuit. The second transistor and the third transistor are configured to provide a current to the latch circuit in response to the first signal.

Abstract: The present application discloses a method for preparing a semiconductor device including an electronic fuse control circuit. The method includes providing a chip including an electronic fuse control circuit, wherein the electronic fuse control circuit includes a program voltage pad, a fuse element, a latch, a plurality of resistor selection pads, and a plurality of bonding option units. The method further includes providing a substrate including a first voltage bonding pad and a plurality of second voltage bonding pads, disposing the chip on the substrate, bonding the first voltage bonding pad to the program voltage pad, and bonding at least one of the plurality of second voltage bonding pads to at least one of the plurality of resistor selection pads.

Abstract: The present application discloses an electronic fuse control circuit, a semiconductor device and a method for forming a semiconductor device including an electronic fuse control circuit. The electronic fuse control circuit includes a program voltage pad, a fuse element, a latch, an operation switch unit, resistor selection pads, and bonding option units. The fuse element includes a first terminal coupled to the program voltage pad, and a second terminal. The operation switch unit forms an electrical connection between the second terminal of the fuse element and a ground terminal during a program operation, and forms an electrical connection between the second terminal of the fuse element and an input terminal of the latch during a read operation. Each of the bonding option units includes a resistor and a selection switch coupled in series between the input terminal of the latch and a resistor selection pad.

Abstract: A semiconductor package includes a package substrate, a semiconductor chip and a plurality of bonding wires. The package substrate includes a connection pad. The semiconductor chip is disposed over the package substrate and includes a chip pad, a bonding pad, and a redistribution layer. The bonding pad is closer to a periphery of the semiconductor chip than the chip pad. The redistribution layer is connected between the chip pad and the bonding pad. The bonding wires are connected in parallel between the connection pad and the bonding pad.