Abstract: A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack.

Abstract: A computing device has a database replica comprised of a plurality of records. A synchronization request is provided to a further computing device having a further database replica which is comprised of a further plurality of records. A version table maintains version numbers for each of the plurality of records. The version numbers each have a maximum size. The maximum size is selectable. The plurality of records may be synchronized with the further plurality of records based upon the version numbers.

Abstract: A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack.

Abstract: A proxy strategy not only caches objects but actively sets update schedules for channel information disseminated from different servers. Based on available bandwidth, this proxy strategy formulates a mathematical function that can be solved to establish the proxy update schedules by maximizing the overall currency of information received by the clients. Clients whose update requests do not result in receiving the most upto-date information for a given channel may also be recorded. After the next scheduled proxy update for a given channel, the proxy actively sends the most up-to-date information for this channel to the recorded clients. The client interest for a given channel is measured based on the client updates the proxy received since last scheduled update for this channel, and the currency of information received by these clients. A dynamic update can be performed by the proxy for channels with high client interest before their respective scheduled updates based on the available bandwidth.

Abstract: A method is provided to form a split-gate flash memory not susceptible to inadvertent reverse tunneling during programming. This is accomplished by forming a silicon nitride spacer on the negatively tapered walls of the floating gate of the cell which serves as a barrier to reverse tunneling. The negatively tapered walls, in contrast to vertical walls, is disclosed to provide a geometry better suited for forming thicker spacers around the floating gate, which in turn serve to act as a more robust barrier to reverse tunneling. Furthermore, it is shown that the method requires fewer steps than practiced in prior art.

Abstract: A device is intended to monitor the paper shredding action of a paper shredder and composed of two paper guiding grid plates, a microswitch, and a detecting rod. A paper guiding passage is formed between the two grid plates. A first paper guiding grid plate is provided with a fastening seat. The detecting rod is fastened pivotally with the fastening seat such that the detecting rod extends between the two paper guiding grid plates. The microswitch is mounted on the fastening seat such that the microswitch is contiguous to the detecting rod. As the front end of a paper sheet has passed the paper guiding passage, the detecting rod is pushed by the front end of the paper sheet to swivel to trigger the microswitch to activate the shredding tools of the paper shredder.

Abstract: A method is achieved for preventing oxide loss on the top corners of the isolation trenches and minimizing parasitic current leakage of the active devices on the substrate. The method consists of forming shallow trenches having either stepped or tapered walls in a silicon substrate using a pad oxide and silicon nitride mask. The dielectric material used to fill the trenches is then etched to form nitride spacers, which protect the top corners of the trench walls from subsequent etching but are removed prior to cleaning of the pad and forming of gate oxide around the trenches.

Abstract: A method is provided to form a split-gate flash memory not susceptible to inadvertent reverse tunneling during programming. This is accomplished by forming a silicon nitride spacer on the negatively tapered walls of the floating gate of the cell which serves as a barrier to reverse tunneling. The negatively tapered walls, in contrast to vertical walls, is disclosed to provide a geometry better suited for forming thicker spacers around the floating gate, which in turn serve to act as a more robust barrier to reverse tunneling. Furthermore, it is shown that the method requires fewer steps than practiced in prior art.

Abstract: A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias.

Abstract: A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias.

Abstract: A paper shredder comprises a housing in which a paper cutting apparatus, a driving device, a link mechanism, and a pencil sharpening apparatus are disposed. The housing is provided with a paper feeding port and a through hole. Paper is fed into the paper shredder via the paper feeding port. A pencil is inserted into an aperture of the pencil sharpening apparatus via the through hole of the housing. The pencil sharpening apparatus comprises a gear and a cutter meshing with the gear such that the cutter is actuated by the gear to sharpen the pencil that is inserted into the aperture of the pencil sharpening apparatus.

Abstract: A method to create raised landing pads for gate electrodes. A layer of polysilicon is deposited over the gate electrode after the gate spacers and the gate isolation areas have been formed. The gate electrode contains two layers, that is a bottom layer of poly and a top layer of oxide or SOG. A layer of photo resist is deposited over the polysilicon, a pattern of landing pads is created in the photo resist. The layer of polysilicon is etched in accordance with the pattern in the photo resist thus forming the elevated landing pads. Source and drain areas of the gate electrode can be contacted by metallic contacts that are in interconnects with these landing pads. The top layer of the gate electrode is removed making the gate electrode a recessed electrode. The invention thereby provides an easy method for removing (by CMP) any bridging that might occur (between the gate electrode and the landing pads) during salicidation.

Abstract: A method for forming a semiconductor device having air regions, the method comprises providing a base, forming a pattern of metal leads, depositing a layer of oxide over the metal leads, forming a layer of nitride over said layer of oxide, opening and etching a trench down to the base layer of material, and depositing and planarizing a dielectric layer. An alternate approach teaches the deposition of a layer of SOG over the layer of oxide that has been deposited over the metal leads, planarizing this layer of SOG down to the top of the metal leads, depositing a layer of PECVD oxide, patterning and etching this layer of PECVD oxide thereby creating openings that are in between the metal leads. The SOG that is between the metal leads can be removed thereby creating air gaps as the intra-level dielectric for the metal leads.

Abstract: A paper feeding sensor mounted in the paper shredder is composed of a microswitch and a detection rod capable of triggering the microswitch so as to actuate two cutters of the paper shredder. The detection rod is received in a receiving cell of the paper guiding grid plate of the paper shredder such that the detection rod is pushed to trigger the microswitch by a paper which is fed into the receiving cell of the paper guiding grid plate.

Abstract: The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 .ANG. to 500 .ANG., and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 .mu.m.

Abstract: A plasma density monitor is described for determining the ion current of a plasma flowing through a conduit (14). The monitor comprises a plate (18) having a face and an orifice extending from the face through the plate. The internal surface of the orifice conforms with the internal surface of the conduit when the face is adjacent the conduit. The monitor also comprises a detector circuit (22) for sensing the ion current collected by the internal surface of the plate (18). Another embodiment monitors plasma density by determining electrical conductivity in the afterglow of a microwave induced plasma. A resonant LC circuit (50, C3) has a multi-turn coil (C3) surrounding the conduit, an RF oscillator circuit (54, 56) for driving the LC circuit, and a circuit (64, 66, 68, 70, 72, 76) for measuring the decay time of the LC circuit. Plasma flowing through the conduit alters the resistivity of the coil and the time constant of the LC circuit proportional to the electrical conductivity of the flowing plasma.

Abstract: A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the integrated circuit patterned and etched to form an opening with substantially vertical sidewalls exposing a portion of an upper surface of a substrate underlying the field oxide where an active area will be formed. A gate electrode comprising a polysilicon gate electrode and a gate oxide are formed over the exposed portion of the substrate. The polysilicon gate has a height at its upper surface above the substrate at or above the height of the upper surface of the field oxide. The gate electrode preferably also comprises a silicide above the polysilicon and an oxide capping layer above the silicide. LDD regions are formed in the substrate adjacent the gate electrode and sidewall spacers are formed along the sides of the gate electrode including the silicide and the capping layer.

Abstract: The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 .ANG. to 500 .ANG., and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 .mu.m.

Abstract: A method for planarization of an integrated circuit. After a first conducting layer is deposited and patterned, a first insulating layer is deposited over the device. A planarizing layer is then deposited over the integrated circuit and etched back. Portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the device. A second insulating layer is then deposited over the integrated circuit, followed by a third insulating layer. A contact via is formed through the layers to expose a portion of the first conducting layer. A second conducting layer can now be deposited and patterned on the device to make electrical contact with the first conducting layer.