Patents by Inventor Xia Li

Xia Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method, device and apparatus for determining time information
    Patent number: 11476962
    Abstract: The present application discloses a method for determining time information, including: detecting a signal of a periodic block, and recording a timestamp of the periodic block; and determining a time at which a time information message to be sent according to the timestamp of the periodic block matched with the time information message, and generating a timestamp of the time information message. The present application further discloses an apparatus and device for determining time information, and a storage medium.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 18, 2022
    Assignee: ZTE CORPORATION
    Inventors: Li He, Xia Li
  • THREE DIMENSIONAL (3D) VERTICAL SPIRAL INDUCTOR AND TRANSFORMER
    Publication number: 20220328237
    Abstract: Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.
    Type: Application
    Filed: April 9, 2021
    Publication date: October 13, 2022
    Inventors: Xia LI, Bin YANG, Haining YANG
  • EVALUATING VISUAL QUALITY OF DIGITAL CONTENT
    Publication number: 20220301141
    Abstract: Systems, devices, methods, and computer readable medium for evaluating visual quality of digital content are disclosed. Methods can include training machine learning models on images. A request is received to evaluate quality of an image included in a current version of a digital component generated by the computing device. The machine learning models are deployed on the image to generate a score for each quality characteristic of the image. A weight is assigned to each score to generate weighted scores. The weighted scores are combined to generate a combined score for the image. The combined score is compared to one or more thresholds to generate a quality of the image.
    Type: Application
    Filed: August 6, 2020
    Publication date: September 22, 2022
    Inventors: Catherine Shyu, Xiyang Luo, Feng Yang, Junjie Ke, Yicong Tian, Chao-Hung Chen, Xia Li, Luying Li, Wenjing Kang, Shun-Chuan Chen
  • COMPOUND, MATERIAL FOR AN ORGANIC ELECTROLUMINESCENT DEVICE AND APPLICATION THEREOF
    Publication number: 20220293861
    Abstract: The present disclosure relates to a compound, a material for an organic electroluminescent device and an application thereof. The compound has a structure represented by Formula (1). The compound has a relatively high refractive index in the region of visible light (400-750 nm), which is conducive to improving the light-emitting efficiency.
    Type: Application
    Filed: September 2, 2021
    Publication date: September 15, 2022
    Inventors: Wenpeng DAI, Wei GAO, Lei Zhang, Lu ZHAI, Xia Li
  • POWER DECOUPLING METAL-INSULATOR-METAL CAPACITOR
    Publication number: 20220293513
    Abstract: Disclosed are examples of a device including a front side metallization portion having a front side BEOL. The device also includes a backside BEOL. The device also includes a substrate, where the substrate is disposed between the backside BEOL and the front side metallization portion. The device also includes a metal-insulator-metal (MIM) capacitor embedded in the backside BEOL.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Inventors: Xia LI, Bin YANG, Haining YANG
  • Distributed feedback (DFB) laser on silicon and integrated device comprising a DFB laser on silicon
    Patent number: 11437781
    Abstract: A distributed feedback (DFB) laser that includes a substrate comprising a first surface and a second surface, wherein the substrate comprises silicon; a plurality of shallow trench isolations (STIs) located over the second surface of the substrate; a grating region located over the plurality of STIs and the substrate, wherein the grating region comprises a III-V semiconductor material; a non-intentional doping (NID) region located over the grating region; and a contact region located over the NID region.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: September 6, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Gengming Tao, Bin Yang, Xia Li
  • Chaotic stirring device and method combining plasma arc smelting and permanent magnet
    Patent number: 11428471
    Abstract: A chaotic stirring device combining plasma arc smelting and permanent magnet including a furnace body; the furnace body is provided therein with a water-cooled copper crucible; the center of an upper surface of the water-cooled copper crucible is a groove for placing raw metals, and the water-cooled copper crucible is internally a hollow cavity; a return pipe is disposed directly below the groove in the hollow cavity; an upper end of the return pipe is vertical upward, and is horizontally provided with a filter screen; a spherical magnet is placed between the filter screen and the groove; one side of the water-cooled copper crucible is provided with a first water inlet pipe and a first water outlet pipe; the first water inlet pipe is connected to the hollow cavity, and the first water outlet pipe is connected to the bottom of the return pipe.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 30, 2022
    Assignee: SHANGHAI UNIVERSITY
    Inventors: Jianbo Yu, Zhongming Ren, Xia Li, Zhenqiang Zhang, Jiang Wang, Yujia Zhang
  • P-TYPE FIELD EFFECT TRANSISTOR (PFET) ON A SILICON GERMANIUM (GE) BUFFER LAYER TO INCREASE GE IN THE PFET SOURCE AND DRAIN TO INCREASE COMPRESSION OF THE PFET CHANNEL AND METHOD OF FABRICATION
    Publication number: 20220271162
    Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.
    Type: Application
    Filed: February 19, 2021
    Publication date: August 25, 2022
    Inventors: Bin Yang, Xia Li, Haining Yang
  • Integrated device comprising transistor coupled to a dummy gate contact
    Patent number: 11404414
    Abstract: An integrated device that includes a substrate, a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is directly electrically coupled to only the gate.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: August 2, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Haining Yang, Xia Li, Bin Yang
  • Semiconductor device implemented with buried rails
    Patent number: 11393819
    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with buried rails (e.g., buried power and ground rails). One example semiconductor device generally includes a substrate; a first rail, wherein a portion of the first rail is disposed in the substrate, the portion of the first rail having a first width greater than a second width of another portion of the first rail; a second rail, wherein a portion of the second rail is disposed in the substrate, the portion of the second rail having a third width greater than a fourth width of another portion of the second rail; and one or more transistors disposed above the substrate and between the first rail and the second rail.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: July 19, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang, Haining Yang
  • DIRECT STARTING SYNCHRONOUS RELUCTANCE MOTOR ROTOR, MOTOR AND ROTOR MANUFACTURING METHOD
    Publication number: 20220224210
    Abstract: The present disclosure provides a direct starting synchronous reluctance motor rotor, a motor and a rotor manufacturing method. The direct starting synchronous reluctance motor rotor comprises: a rotor core provided with a plurality of slit grooves, two ends of each of the slit grooves being provided with a filling groove respectively to form a magnetic barrier layer, a first end of the filling groove being disposed adjacent to the slit groove, a second end of the filling groove being extended towards an outside of the rotor core, and an outer peripheral surface of the rotor core being provided with a notch communicated with the second end of the filling groove.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 14, 2022
    Applicant: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
    Inventors: Yusheng HU, Bin CHEN, Jinfei SHI, Yong XIAO, Xia LI, Qinhong YU
  • DIRECT STARTING SYNCHRONOUS RELUCTANCE MOTOR ROTOR AND MOTOR
    Publication number: 20220216747
    Abstract: The present disclosure provides a direct starting synchronous reluctance motor rotor, and a motor. The direct starting synchronous reluctance motor rotor comprises: a rotor core provided with a plurality of slit grooves, two filling grooves are respectively disposed at two ends of each of the slit grooves to form a magnetic barrier layer, a first end of the filling groove being disposed adjacent to the slit groove, a second end of the filling groove being disposed to be extended outwards an outside of the rotor core, a beveled edge is disposed on the second end of at least one of the filling grooves away from a d-axis of the rotor core, so that a d-axis flux of the rotor core will not suddenly change when entering a stator along a channel formed at the beveled edge.
    Type: Application
    Filed: December 25, 2019
    Publication date: July 7, 2022
    Applicant: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
    Inventors: Yusheng HU, Bin CHEN, Yong XIAO, Jinfei SHI, Qinhong YU, Xia LI
  • Local active matrix architecture
    Patent number: 11355056
    Abstract: A local active matrix display panel, circuits and methods of operation are described. In an embodiment, a local active matrix display panel includes an array of pixel driver chip, a thin film transistor layer in electrical contact with the array of pixel driver chips, and an array of light emitting diodes electrically connected with the thin film transistor layer.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: June 7, 2022
    Assignee: Apple Inc.
    Inventors: Hjalmar Edzer Ayco Huitema, Thomas Charisoulis, Xia Li
  • SELF-ALIGNED LOW RESISTANCE BURIED POWER RAIL THROUGH SINGLE DIFFUSION BREAK DUMMY GATE
    Publication number: 20220173039
    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a buried power rail (BPR) having decreased resistance and a method of fabricating such a semiconductor device with a BPR. An example semiconductor device generally includes a substrate, a first transistor structure disposed above the substrate, a second transistor structure disposed above the substrate, and a BPR structure disposed between the first transistor structure and the second transistor structure. The BPR structure generally includes at least two distinguishable portions, which may be a first portion disposed above a second portion, the second portion having a greater width than the first portion.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 2, 2022
    Inventors: Bin YANG, Haining YANG, Xia LI
  • SELF-STARTING SYNCHRONOUS RELUCTANCE MOTOR ROTOR, MOTOR, AND COMPRESSOR
    Publication number: 20220173644
    Abstract: The present disclosure is related to a self-starting synchronous reluctance motor rotor, a motor and a compressor. The self-starting synchronous reluctance motor rotor includes a rotor core; the rotor core is provided with a plurality of slit grooves; both ends of each of the slit grooves are respectively provided with a filled groove; a first end of the filled groove is provided adjacent to each slit groove, and a second end of the filled groove extends outwards parallel to the d-axis of the rotor core; the second end of the filled groove is provided with at least one bevel edge, so that when the d-axis magnetic flux of the rotor core enters a stator along channels formed at the bevel edges, no abrupt change occurs to the magnetic flux.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 2, 2022
    Applicant: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
    Inventors: Xia LI, Bin CHEN, Jinfei SHI, Yong XIAO, Qinhong YU
  • Synergistic effects of multi-faceted CU2O nanocrystals for electrochemical CO2 reduction
    Patent number: 11339487
    Abstract: A method of electrochemical reduction of carbon dioxide includes the use of multi-faceted Cu2O crystals as a catalyst to convert CO2 to value-added products. An electrochemical cell for the electrochemical reduction of carbon dioxide includes a cathode including the multi-faceted Cu2O crystals. The multi-faceted Cu2O crystals have at least two different types of facets with different Miller indices. The multi-faceted Cu2O crystals include steps and kinks present at the transitions between the different types of facets. These steps and kinks improve the Faradaic Efficiency of the conversion of carbon dioxide. The multi-faceted Cu2O crystals may be nanosized. The multi-faceted Cu2O crystals may include 18-facet, 20-facet, and/or 50-facet Cu2O crystals.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: May 24, 2022
    Assignees: HONDA MOTOR CO., LTD., UTAH STATE UNIVERSITY
    Inventors: Gugang Chen, Yi Rao, Xia Li
  • Compute-in-memory (CIM) binary multiplier
    Patent number: 11340867
    Abstract: Certain aspects provide methods and apparatus for binary computation. An example circuit for such computation generally includes a memory cell having at least one of a bit-line or a complementary bit-line; a computation circuit coupled to a computation input node of the circuit and the bit-line or the complementary bit-line; and an adder coupled to the computation circuit, wherein the computation circuit comprises a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the adder, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: May 24, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Zhongze Wang, Periannan Chidambaram
  • Compute-in-memory (CIM) cell circuits employing capacitive storage circuits for reduced area and CIM bit cell array circuits
    Patent number: 11322199
    Abstract: A CIM bit cell circuit employing a capacitive storage circuit to store a binary weight data as a voltage occupies half or less of the area of a 6T SRAM CIM bit cell circuit, reducing the increase in area incurred in the addition of a CIM bit cell array circuit to an IC. The CIM bit cell circuit includes a capacitive storage circuit that stores binary weight data in a capacitor and generates a product voltage indicating a binary product resulting from a logical AND-based operation of the stored binary weight data and an activation signal. The capacitive storage circuit may include a capacitor and a read access switch or a transistor. The CIM bit cell circuit includes a write access switch to couple a write bit voltage to the capacitive storage circuit. In a CIM bit cell array circuit, the product voltages are summed in a MAC operation.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: May 3, 2022
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • MULTI-CHANNEL GATE-ALL-AROUND HIGH-ELECTRON-MOBILITY TRANSISTOR
    Publication number: 20220131013
    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device implemented with multiple channels in a gate-all-around (GAA) high-electron-mobility transistor (HEMT) and techniques for fabricating such a device. One example semiconductor device generally includes a substrate; a first gate layer disposed above the substrate; a first barrier layer disposed above the first gate layer; a first channel region disposed above the first barrier layer; a second barrier layer disposed above the first channel region; a second gate layer disposed above the second barrier layer; a third barrier layer disposed above the second gate layer; a second channel region disposed above the third barrier layer; a fourth barrier layer disposed above the second channel region; a source region; and a drain region.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 28, 2022
    Inventors: Chenjie TANG, Gengming TAO, Ye LU, Bin YANG, Xia LI
  • Cabinet
    Patent number: D949606
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: April 26, 2022
    Inventor: Xia Li