Patents by Inventor Xiangfeng Duan

Xiangfeng Duan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150318401
    Abstract: A vertically stacked heterostructure device includes: (1) a substrate; and (2) vertically stacked layers disposed over the substrate and including (a) a source electrode including a layer of graphene; (b) a drain electrode; and (c) a semiconducting channel disposed between the source electrode and the drain electrode. During operation of the device, a current is configured to flow between the source electrode and the drain electrode through the semiconducting channel.
    Type: Application
    Filed: December 20, 2013
    Publication date: November 5, 2015
    Inventors: Xiangfeng Duan, Woojong Yu, Yuan Liu, Yu Huang
  • Patent number: 9012882
    Abstract: A graphene nanomesh includes a sheet of graphene having a plurality of periodically arranged apertures, wherein the plurality of apertures have a substantially uniform periodicity and substantially uniform neck width. The graphene nanomesh can open up a large band gap in a sheet of graphene to create a semiconducting thin film. The periodicity and neck width of the apertures formed in the graphene nanomesh may be tuned to alter the electrical properties of the graphene nanomesh. The graphene nanomesh is prepared with block copolymer lithography. Graphene nanomesh field-effect transistors (FETs) can support currents nearly 100 times greater than individual graphene nanoribbon devices and the on-off ratio, which is comparable with values achieved in nanoribbon devices, can be tuned by varying the neck width. The graphene nanomesh may also be incorporated into FET-type sensor devices.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: April 21, 2015
    Assignee: The Regents of the University of California
    Inventors: Xiangfeng Duan, Yu Huang, Jingwei Bai
  • Patent number: 8981452
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing also are provided.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: March 17, 2015
    Assignee: SanDisk Corporation
    Inventors: Jian Chen, Xiangfeng Duan, Chao Liu, Madhuri Nallabolu, J. Wallace Parce, Srikanth Ranganathan
  • Patent number: 8871623
    Abstract: Methods are provided for forming a nanostructure array. An example method includes providing a first layer, providing nanostructures dispersed in a solution comprising a liquid form of a spin-on-dielectric, wherein the nanostructures comprise a silsesquioxane ligand coating, disposing the solution on the first layer, whereby the nanostructures form a monolayer array on the first layer, and curing the liquid form of the spin-on-dielectric to provide a solid form of the spin-on-dielectric. Numerous other aspects are provided.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: October 28, 2014
    Assignee: SanDisk Corporation
    Inventors: Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Publication number: 20140206182
    Abstract: Methods are provided for forming a nanostructure array. An example method includes providing a first layer, providing nanostructures dispersed in a solution comprising a liquid form of a spin-on-dielectric, wherein the nanostructures comprise a silsesquioxane ligand coating, disposing the solution on the first layer, whereby the nanostructures form a monolayer array on the first layer, and curing the liquid form of the spin-on-dielectric to provide a solid form of the spin-on-dielectric. Numerous other aspects are provided.
    Type: Application
    Filed: April 11, 2014
    Publication date: July 24, 2014
    Applicant: SanDisk Corporation
    Inventors: Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Patent number: 8735226
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: May 27, 2014
    Assignee: SanDisk Corporation
    Inventors: Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Publication number: 20140077161
    Abstract: A graphene transistor includes: (1) a substrate; (2) a source electrode disposed on the substrate; (3) a drain electrode disposed on the substrate; (4) a graphene channel disposed on the substrate and extending between the source electrode and the drain electrode; and (5) a top gate disposed on the graphene channel and including a nanostructure.
    Type: Application
    Filed: March 2, 2012
    Publication date: March 20, 2014
    Inventors: Xiangfeng Duan, Yu Huang, Lei Liao, Jingwei Bai
  • Publication number: 20140042390
    Abstract: An interpenetrating network assembly with a network of connected flakes of nano-scale crystalline carbon and nano-scale particles of an electroactive material interconnected with the carbon flakes is provided. The network assemblies are particularly suited for energy storage applications that use metal oxide electroactive materials and a single charge collector or a source and drain. Interpenetrating networks of graphene flakes and metal oxide nanosheets can form independent pathways between source and drain. Nano-scale conductive materials such as metal nanowires, carbon nanotubes, activated carbon or carbon black can be included as part of the conductive network to improve charge transfer.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 13, 2014
    Applicant: THE REGENTS OF UNIVERSITY OF CALIFORNIA
    Inventors: George Gruner, Xiangfeng Duan, Bruce S. Dunn, Veronica Augustyn
  • Publication number: 20140035011
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing also are provided.
    Type: Application
    Filed: September 20, 2013
    Publication date: February 6, 2014
    Applicant: SANDISK CORPORATION
    Inventors: Jian Chen, Xiangfeng Duan, Chao Liu, Madhuri Nallabolu, J. Wallace Parce, Srikanth Ranganathan
  • Publication number: 20130337642
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
    Type: Application
    Filed: August 1, 2013
    Publication date: December 19, 2013
    Applicant: SanDisk 3D LLC
    Inventors: Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Patent number: 8558304
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: October 15, 2013
    Assignee: SanDisk Corporation
    Inventors: Jian Chen, Xiangfeng Duan, Chao Liu, Madhuri Nallabolu, J. Wallace Parce, Srikanth Ranganathan
  • Patent number: 8507390
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: August 13, 2013
    Assignee: Sandisk Corporation
    Inventors: Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Publication number: 20120329251
    Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 27, 2012
    Applicant: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Jiangtao Hu
  • Publication number: 20120301953
    Abstract: A graphene nanomesh includes a sheet of graphene having a plurality of periodically arranged apertures, wherein the plurality of apertures have a substantially uniform periodicity and substantially uniform neck width. The graphene nanomesh can open up a large band gap in a sheet of graphene to create a semiconducting thin film. The periodicity and neck width of the apertures formed in the graphene nanomesh may be tuned to alter the electrical properties of the graphene nanomesh. The graphene nanomesh is prepared with block copolymer lithography. Graphene nanomesh field-effect transistors (FETs) can support currents nearly 100 times greater than individual graphene nanoribbon devices and the on-off ratio, which is comparable with values achieved in nanoribbon devices, can be tuned by varying the neck width. The graphene nanomesh may also be incorporated into FET-type sensor devices.
    Type: Application
    Filed: January 28, 2011
    Publication date: November 29, 2012
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xiangfeng Duan, Yu Huang, Jingwei Bai
  • Patent number: 8252164
    Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: August 28, 2012
    Assignees: Nanosys, Inc., Sharp Kabushiki Kaisha
    Inventors: Samuel Martin, Xiangfeng Duan, Katsumasa Fujii, James M. Hamilton, Hiroshi Iwata, Francisco Leon, Jeffrey Miller, Tetsu Negishi, Hiroshi Ohki, J. Wallace Parce, Cheri X. Y. Pereira, Paul John Schuele, Akihide Shibata, David P. Stumbo, Yasunobu Okada
  • Patent number: 8153470
    Abstract: A method for selectively aligning and positioning semiconductor nanowires on a substrate by providing a substrate; patterning electrodes on a surface of the substrate; conditioning the surface of the substrate to attach semiconductor nanowires to the surface by functionalizing the surface with a first functional group having an affinity for the semiconductor nanowires; providing an environment in contact with the electrodes, the environment having suspended therein the semiconductor nanowires; and providing an electric field between the electrodes, thereby causing the nanowires in the environment to align between and electrically connect the electrodes to thereby form a semiconducting channel between the electrodes.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: April 10, 2012
    Assignee: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Yu Huang
  • Patent number: 8143703
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: March 27, 2012
    Assignee: Nanosys, Inc.
    Inventors: David L. Heald, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Publication number: 20110284380
    Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.
    Type: Application
    Filed: May 23, 2011
    Publication date: November 24, 2011
    Inventors: Samuel MARTIN, Xiangfeng Duan, Katsumasa Fujii, James M. Hamilton, Hiroshi Iwata, Francisco Leon, Jeffrey Miller, Tetsu Negishi, Hiroshi Ohki, J. Wallace Parce, Cheri X.Y. Pereira, Paul John Schuele, Akihide Shibata, David P. Stumbo, Yasunobu Okada
  • Patent number: 8030161
    Abstract: A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: October 4, 2011
    Assignee: Nanosys, Inc.
    Inventors: Xiangfeng Duan, Jian Chen, J. Wallace Parce, Francisco A. Leon
  • Publication number: 20110204432
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.
    Type: Application
    Filed: April 29, 2011
    Publication date: August 25, 2011
    Applicant: NANOSYS, INC.
    Inventors: Jian Chen, Xiangfeng Duan, Chao Liu, Madhuri L. Nallabolu, J. Wallace Parce, Srikanth Ranganathan