Patents by Inventor Xiangfeng Duan

Xiangfeng Duan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7985454
    Abstract: The present invention is directed to compositions of matter, systems, and methods to manufacture nanowires. In an embodiment, a method to produce a catalytic-coated nanowire growth substrate for nanowire growth is disclosed which comprises: (a) depositing a buffer layer on a substrate; (b) treating the buffer layer with boiled water or steam to enhance interactions between the buffer layer and catalyst particles; and (c) depositing catalytic particles on a surface of the buffer layer. Methods to develop and use this catalytic-coated nanowire growth substrate are disclosed.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: July 26, 2011
    Assignee: Nanosys, Inc.
    Inventors: Chunming Niu, Jay L. Goldman, Xiangfeng Duan, Vijendra Sahi
  • Patent number: 7968474
    Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: June 28, 2011
    Assignees: Nanosys, Inc., Sharp Kabushiki Kaisha
    Inventors: Samuel Martin, Xiangfeng Duan, Katsumasa Fujii, James M. Hamilton, Hiroshi Iwata, Francisco Leon, Jeffrey Miller, Tetsu Negishi, Hiroshi Ohki, J. Wallace Parce, Cheri X. Y. Pereira, Paul John Schuele, Akihide Shibata, David P. Stumbo, Yasunobu Okada
  • Patent number: 7968273
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: June 28, 2011
    Assignee: Nanosys, Inc.
    Inventors: Jian Chen, Xiangfeng Duan, Chao Liu, Madhuri L. Nallabolu, J. Wallace Parce, Srikanth Ranganathan
  • Patent number: 7951422
    Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors, as well as us of patterned substrates to grow oriented nanowires. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: May 31, 2011
    Assignee: Nanosys, Inc.
    Inventors: Yaoling Pan, Xiangfeng Duan, Robert S. Dubrow, Jay Goldman, Shahriar Mostarshed, Chunming Niu, Linda T. Romano, David P. Stumbo, Alice Fischer-Colbrie, Vijendra Sahi, Virginia Robbins
  • Patent number: 7932511
    Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: April 26, 2011
    Assignee: Nanosys, Inc.
    Inventors: Xiangfeng Duan, Chunming Niu, Stephen Empedocles, Linda T. Romano, Jian Chen, Vijendra Sahi, Lawrence Bock, David Stumbo, J. Wallace Parce, Jay L. Goldman
  • Patent number: 7915151
    Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: March 29, 2011
    Assignee: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Yu Huang
  • Publication number: 20110034038
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
    Type: Application
    Filed: June 29, 2010
    Publication date: February 10, 2011
    Applicant: NANOSYS, Inc.
    Inventors: Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Patent number: 7851841
    Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: December 14, 2010
    Assignee: Nanosys, Inc.
    Inventors: Xiangfeng Duan, Chunming Niu, Stephen A. Empedocles, Linda T. Romano, Jian Chen, Vijendra Sahi, Lawrence Bock, David P. Stumbo, J. Wallace Parce, Jay L. Goldman
  • Publication number: 20100279513
    Abstract: The present invention is directed to compositions of matter, systems, and methods to manufacture nanowires. In an embodiment, a buffer layer is placed on a nanowire growth substrate and catalytic nanoparticles are added to form a catalytic-coated nanowire growth substrate. Methods to develop and use this catalytic-coated nanowire growth substrate are disclosed. In a further aspect of the invention, in an embodiment a nanowire growth system using a foil roller to manufacture nanowires is provided.
    Type: Application
    Filed: September 23, 2008
    Publication date: November 4, 2010
    Applicant: NANOSYS, INC.
    Inventors: Chunming Niu, Jay L. Goldman, Xiangfeng Duan, Vijendra Sahi
  • Publication number: 20100261013
    Abstract: The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.
    Type: Application
    Filed: June 22, 2010
    Publication date: October 14, 2010
    Applicant: NANOSYS, INC.
    Inventors: Xiangfeng Duan, Chunming Niu, Stephen A. Empedocles, David P. Stumbo
  • Patent number: 7776758
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: August 17, 2010
    Assignee: Nanosys, Inc.
    Inventors: Xiangfeng Duan, Chao Liu
  • Publication number: 20100155698
    Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components.
    Type: Application
    Filed: June 26, 2009
    Publication date: June 24, 2010
    Applicant: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Xiangfeng Duan, Yi Cui, Yu Huang, Mark Gudiksen, Lincoln J. Lauhon, Jianfang Wang, Hongkun Park, Qingqiao Wei, Wenjie Liang, David C. Smith, Deli Wang, Zhaohui Zhong
  • Publication number: 20100155696
    Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
    Type: Application
    Filed: March 1, 2007
    Publication date: June 24, 2010
    Applicant: NANOSYS, INC.
    Inventors: Xiangfeng Duan, Chunming Niu, Stephen Empedocles, Linda T. Romano, Jian Chen, Vijendra Sahi, Lawrence Bock, David Stumbo, J. Wallace Parce, Jay L. Goldman
  • Publication number: 20100155786
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.
    Type: Application
    Filed: July 27, 2007
    Publication date: June 24, 2010
    Applicant: NANOSYS, Inc.
    Inventors: David L. Heald, Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, Madhuri L. Nallabolu, J. Wallace Parce, Srikanth Ranganathan
  • Patent number: 7741197
    Abstract: The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: June 22, 2010
    Assignee: Nanosys, Inc.
    Inventors: Xiangfeng Duan, Paul Bernatis, Alice Fischer-Colbrie, James M. Hamilton, Francesco Lemmi, Yaoling Pan, J. Wallace Parce, Cheri X. Y. Pereira, David P. Stumbo
  • Publication number: 20100093158
    Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 15, 2010
    Applicant: President and fellows of Harvard College
    Inventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Yu Huang
  • Patent number: 7666708
    Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal is, axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less an 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety assembling techniques may be used to fabricate devices from such a semiconductor.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: February 23, 2010
    Assignee: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Yu Huang
  • Patent number: 7651944
    Abstract: Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures, devices that include populations of positioned and/or oriented nanostructures, systems for positioning and/or orienting nanostructures, and related devices, systems and methods.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: January 26, 2010
    Assignee: Nanosys, Inc.
    Inventors: Xiangfeng Duan, R. Hugh Daniels, Chunming Niu, Vijendra Sahi, James M. Hamilton, Linda T. Romano
  • Publication number: 20090278125
    Abstract: The present invention describes an approach to grow highly crystalline semiconductor films, multilayers of semiconductor thin films on foreign substrate such as glass, quartz. Specifically, The film were grown by first forming crystalline seeds, and transferring the seeds onto the substrate, and growing continuous semiconductor film through epitaxial growth on the seeds.
    Type: Application
    Filed: April 17, 2009
    Publication date: November 12, 2009
    Inventors: Xiangfeng Duan, Xidong Duan
  • Patent number: 7595260
    Abstract: A bulk-doped semiconductor may be at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may have a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: September 29, 2009
    Assignee: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Yu Huang