Patents by Inventor Xiao Hong
Xiao Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080113547Abstract: An exemplary orienting structure includes two locating units, a first supporting bump, and a second supporting bump. Each of the locating units includes a first portion and a second portion perpendicular to the first portion. The first supporting bump and the locating units cooperatively define a sliding track configured for slidingly receiving a male connector. A female connector is disposed on the second supporting bump and aligned with the sliding track. The first portions of the locating units function as guides for blocking movement along a first axis of the sliding track. The first supporting bump in cooperation with the second portions of the locating units function as guides for blocking movement along a second axis of the sliding track. When the male connector is slid along the sliding track, the sliding is in a direction perpendicular to both the first and second axes of the sliding track.Type: ApplicationFiled: November 13, 2007Publication date: May 15, 2008Inventor: Xiao-Hong Jing
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Patent number: 7313010Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: GrantFiled: June 23, 2006Date of Patent: December 25, 2007Assignee: Ramtron International CorporationInventors: Shan Sun, Xiao-Hong Du, Fan Chu, Bob Sommervold
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Patent number: 7271744Abstract: An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n?1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.Type: GrantFiled: December 14, 2006Date of Patent: September 18, 2007Assignee: Ramtron InternationalInventors: Xiao Hong Du, Dennis C. Young
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Patent number: 7233194Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.Type: GrantFiled: October 9, 2003Date of Patent: June 19, 2007Assignee: Texas Instruments IncorporatedInventors: Xiao Hong Du, Jarrod Eliason, Yunchen Qiu, Bill Kraus
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Patent number: 7214534Abstract: The invention provides genetic approaches to inhibit or treat pain which employ mutant ? opioid receptors.Type: GrantFiled: June 18, 2003Date of Patent: May 8, 2007Assignee: Regents of the University of MinnesotaInventors: Ping-yee Law, Horace H. Loh, Wanling Yang, Xiao-Hong Guo, Patricia A. Geppert
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Patent number: 7176824Abstract: An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n?1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.Type: GrantFiled: November 21, 2003Date of Patent: February 13, 2007Assignee: Ramtron InternationalInventors: Xiao Hong Du, Dennis C. Young
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Publication number: 20070002275Abstract: A local adaptive method is proposed for automatic detection of microaneurysms in a digital ocular fundus image. Multiple subregions of the image are automatically analyzed and adapted to local intensity variation and properties. A priori region and location information about structural features such as vessels, optic disk and hard exudates are incorporated to further improve the detection accuracy. The method effectively improves the specificity of microaneurysms detection, without sacrificing sensitivity. The method may be used in automatic level-one grading of diabetic retinopathy screening.Type: ApplicationFiled: June 20, 2006Publication date: January 4, 2007Applicant: Siemens Corporate Research Inc.Inventors: Xiao-Hong Yan, Ke Huang, Hans Schull
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Patent number: 7142627Abstract: A counting scheme for a non-volatile counter includes automatic point-of-reference generation implemented in a state machine. Two state variables are used to store the rotation history of the magnet. One variable stores the previous position of the magnet and the other stores the net angle traveled by the magnet from the reference point. The first pulse location after the counter is reset is automatically selected as the reference point until the next counter reset. When the nonvolatile counter counts up or down, i.e. when the magnet travels 360° in either direction, the second state variable is set to zero and the first state variable is set to the reference point, indicating the start of a new revolution.Type: GrantFiled: March 17, 2005Date of Patent: November 28, 2006Assignee: Ramtron International CorporationInventors: Xiao-Hong Du, Craig Taylor
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Publication number: 20060245286Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: ApplicationFiled: June 23, 2006Publication date: November 2, 2006Inventors: Shan SUN, Xiao-Hong Du, Fan Chu, Bob Sommervold
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Patent number: 7120220Abstract: A non-volatile counter circuit includes a state machine having a first input for receiving one or more control signals, a second input for receiving a current count value, a third input for receiving historical information, and an output for providing a next count value and an up/down control signal, and a non-volatile counter having an input coupled to the output of the state machine, and an output for providing a non-volatile count value. The non-volatile counter can be implemented onto a single integrated circuit using ferroelectric memory technology. The non-volatile counter circuit includes a first power supply node and a second power supply node for receiving power for operating the non-volatile-counter circuit through a first power supply or a second power supply, or both. The first and second power supplies can be low energy power supplies such as that provided by a sensor, or can be conventional power supplies.Type: GrantFiled: December 23, 2004Date of Patent: October 10, 2006Assignee: Ramtron International CorporationInventors: Xiao-Hong Du, Craig Taylor
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Patent number: 7116572Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: GrantFiled: November 9, 2004Date of Patent: October 3, 2006Assignee: Ramtron International CorporationInventors: Shan Sun, Xiao-Hong Du, Fan Chu, Bob Sommervold
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Patent number: 7110269Abstract: This invention relates to new soft-switching techniques for minimizing switching losses and stress in power electronic circuits using inverter legs. By choosing the switching frequency with specific relationships with the resonant frequency of the power electronic circuits, the proposed switching technique enables the power electronic circuits to achieve soft switching under full load and short-circuit conditions at the defined frequencies for both capacitive and inductive loads. This technique can be applied to an electronic circuit with two switches connected in totem pole configuration between two dc voltage rails or commonly known as a power inverter leg or inverter arm. Examples of these circuits are class-D power converter, half-bridge power converters and full-bridge power converters or inverters. The proposed techniques allow inverter circuits with resistive, capacitive and inductive loads to achieve soft switching.Type: GrantFiled: August 9, 2005Date of Patent: September 19, 2006Assignee: City University of Hong KongInventors: Xiao Hong Cao, Shu-Yuen Ron Hui
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Publication number: 20060140331Abstract: A non-volatile counter circuit includes a state machine having a first input for receiving one or more control signals, a second input for receiving a current count value, a third input for receiving historical information, and an output for providing a next count value and an up/down control signal, and a non-volatile counter having an input coupled to the output of the state machine, and an output for providing a non-volatile count value. The non-volatile counter can be implemented onto a single integrated circuit using ferroelectric memory technology. The non-volatile counter circuit includes a first power supply node and a second power supply node for receiving power for operating the non-volatile-counter circuit through a first power supply or a second power supply, or both. The first and second power supplies can be low energy power supplies such as that provided by a sensor, or can be conventional power supplies.Type: ApplicationFiled: December 23, 2004Publication date: June 29, 2006Inventors: Xiao-Hong Du, Craig Taylor
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Publication number: 20060140332Abstract: A counting scheme for a non-volatile counter includes automatic point-of-reference generation implemented in a state machine. Two state variables are used to store the rotation history of the magnet. One variable stores the previous position of the magnet and the other stores the net angle traveled by the magnet from the reference point. The first pulse location after the counter is reset is automatically selected as the reference point until the next counter reset. When the nonvolatile counter counts up or down, i.e. when the magnet travels 360° in either direction, the second state variable is set to zero and the first state variable is set to the reference point, indicating the start of a new revolution.Type: ApplicationFiled: March 17, 2005Publication date: June 29, 2006Inventors: Xiao-Hong Du, Craig Taylor
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Publication number: 20060098470Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: ApplicationFiled: November 9, 2004Publication date: May 11, 2006Inventors: Shan Sun, Xiao-Hong Du, Fan Chu, Bob Sommervold
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Patent number: 6915762Abstract: A wall-mountable aquarium has a slim tank for containing water to keep living aquatic animals or plants. The tank includes a transparent front wall, a rear wall, opposite left and right side walls and a bottom wall, with the side and bottom walls being considerably narrower than the front and rear walls. A fixed enclosure is provided externally on at least one of the left and right side walls and bottom wall for containing part of accessory for the aquarium. A frame is attached on the front wall, which conceals the enclosure from direct sight from the front and includes a see-through portion therein to reveal only the living habitat inside the tank through the front wall.Type: GrantFiled: September 8, 2003Date of Patent: July 12, 2005Assignee: Suzhou Good View Aquaria Technology Co., Ltd.Inventors: Han Chang Hsieh, Xiao Hong Liu
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Patent number: 6909318Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to ists source to turn if off during boostenig. Ttransistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.Type: GrantFiled: August 27, 2003Date of Patent: June 21, 2005Assignee: Texas Instruments IncorporatedInventors: Xiao Hong Du, Jarrod Eliason, Yunchen Qiu, Bill Kraus
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Patent number: 6864738Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN1) to charge the boosting capacitor (C1) to VDD at the end of each memory access and to use a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.Type: GrantFiled: January 6, 2003Date of Patent: March 8, 2005Assignee: Texas Instruments IncorporatedInventors: Xiao Hong Du, Jarrod Eliason, Yunchen Qiu, Bill Kraus
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Patent number: D524317Type: GrantFiled: August 26, 2005Date of Patent: July 4, 2006Assignee: Hon Hai Precision Industry Co., LTDInventors: Xiao-Hong Cui, Yun-Dong Xu, Yi Hu
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Patent number: D528121Type: GrantFiled: September 26, 2005Date of Patent: September 12, 2006Assignee: Hon Hai Precision Industry Co., LTDInventors: Yi Hu, Yun-Dong Xu, Xiao-Hong Cui