Abstract: A background setting for an aquarium having front and rear walls and opposite left and right side walls. The setting comprises a water-resistant background sheet bearing a background scenery for direct submersion in the water of the aquarium to cover the rear wall, and a fixture for fixing the background sheet inside the aquarium.

Abstract: This invention relates to new soft-switching techniques for minimizing switching losses and stress in power electronic circuits using inverter legs. By choosing the switching frequency with specific relationships with the resonant frequency of the power electronic circuits, the proposed switching technique enables the power electronic circuits to achieve soft switching under full load and short-circuit conditions at the defined frequencies for both capacitive and inductive loads. This technique can be applied to an electronic circuit with two switches connected in totem pole configuration between two dc voltage rails or commonly known as a power inverter leg or inverter arm. Examples of these circuits are class-D power converter, half-bridge power converters and full-bridge power converters or inverters. The proposed techniques allow inverter circuits with resistive, capacitive and inductive loads to achieve soft switching.

Abstract: A system, method and data unit for automated and secure digital mobile video recording and monitoring are provided where the system includes an authenticated acquisition subsystem for digitally watermarking video data, a video management subsystem in signal communication with the authenticated acquisition subsystem for storing, viewing and verifying the digitally watermarked video data, and a secure wireless video transfer subsystem for signal communication between the acquisition and management subsystems; the method includes digitally watermarking video data, verifying the digitally watermarked video data, and coordinating communications of video data; and the data unit is a digital video data file encoded with signal data having block transform coefficients indicative of a secure digital mobile video recording, the coefficients collectively indicative of an original video data sequence with a secure watermark, the secure watermark including a plurality of signatures.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to ists source to turn if off during boostenig. Ttransistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN1) to charge the boosting capacitor (C1) to VDD at the end of each memory access and to use a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.

Abstract: A hybrid digital watermarking system for video authentication includes an authenticated acquisition subsystem for digitally watermarking video data and a video management subsystem in signal communication with the authenticated acquisition subsystem for verifying the digitally watermarked video data, where the authenticated acquisition subsystem may include a watermarking device for applying each of an identity signature and a control signature to the video data within a hybrid digital watermark, and the hybrid digital watermark may achieve progressively varying robustness by means of error-correcting signature coding and/or rate-distortion guided bit embedding.

Abstract: The invention provides methods for quickly and efficiently detecting receptor-ligand binding, including high throughput, cell-based assay methods. Assay methods for detecting mediators of receptor-ligand binding and for screening cDNA libraries are also provided.

Abstract: The invention provides genetic approaches to inhibit or treat pain which employ mutant &mgr; opioid receptors.

Abstract: A bit-line shielding technique for a ferroelectric memory logically divides the bit-lines in the array into two groups. When the bit-lines in one of the groups are accessed, the bit-lines in the other group are not accessed and thus can be grounded to electrically shield the bit-lines being accessed. Each group of bit-lines is coupled to the drains of a group of pre-charge devices at the bottom of the array. The sources of the pre-charge devices are grounded. The word lines are arranged so that only the bit-lines in one of the groups are accessed at a time.

Abstract: The bicycle trainer includes a frame having a head tube, a top tube, and a rear fork, wherein a foot bar and a front fork are mounted at a lower part of the head tube, a front part of the top tube is pivotally connected to the head tube, and the rear fork is connected to the top tube; a handle connected to the front fork of the frame and properly connected to the front fork; a front wheel and a rear wheel pivotally connected to front wheel and rear wheel; and a flexible device connecting the frame with a rear pivot shaft at one side of the rear wheel, wherein the flexible device drive the rear wheel to rotate and is recovered by using a swirling spring installed at the other side of the rear wheel.

Abstract: The bicycle trainer includes a frame having a head tube, a top tube, and a rear fork, wherein a foot bar and a front fork are mounted at a lower part of the head tube, a front part of the top tube is pivotally connected to the head tube, and the rear fork is connected to the top tube; a handle connected to the front fork of the frame and properly connected to the front fork; a front wheel and a rear wheel pivotally connected to front wheel and rear wheel; and a flexible device connecting the frame with a rear pivot shaft at one side of the rear wheel, wherein the flexible device drive the rear wheel to rotate and is recovered by using a swirling spring installed at the other side of the rear wheel.

Abstract: A switched capacitor circuit 300, including a sampling capacitor 303, switches 301, 304 for charging the sampling capacitor 303 during a charging phase, and switches 302, 305 for transferring charge from the sampling capacitor 303 to a load 313 in the feedback loop of an operational amplifier 312 during a dump phase. Circuitry 701 controls the discharge of sampling capacitor 303 during the dump phase to minimize transients at the input of the operational amplifier 312 and thereby minimize input threshold voltage variation.

Abstract: A novelty item having extending appendages which are supported by springs so as to impart life-like movement thereto.

Abstract: A novelty item having extending appendages which are supported by springs so as to impart life-like movement thereto.

Abstract: A novelty item having extending appendages which are supported by springs so as to impart life-like movement thereto.

Abstract: A novelty item having extending appendages which are supported by springs so as to impart life-like movement thereto.

Abstract: An organic EL device, includes an anode, cathode, and at least one organic luminescent layer including a compound of the formula: 1

Abstract: According to one embodiment, the invention relates to a system and method for evaluating the creditworthiness of an account holder of a credit account comprising the steps of determining, at least once a day, whether a first data set relating to the creditworthiness of the account holder has been received from a credit reporting organization; determining, at least once a day, whether a second data set relating to transaction activity of the credit account has been received; periodically receiving from a credit reporting organization a third data set relating to the creditworthiness of the account holder; periodically receiving a fourth data set relating to the historical activity of the credit account; and using the first and second data sets, to the extent they have been received, and the third and fourth data sets to determine a measure of creditworthiness.