Patents by Inventor Xiaobin Wang

Xiaobin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8054675
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: November 8, 2011
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
  • Patent number: 8054678
    Abstract: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: November 8, 2011
    Assignee: Seagate Technology LLC
    Inventors: Alan Xuguang Wang, Xiaobin Wang, Dimitar V. Dimitrov, Hai Li, Haiwen Xi, Harry Hongyue Liu
  • Patent number: 8048545
    Abstract: A perpendicular magnetic recording medium adapted for high recording density and high data recording rate comprises a non-magnetic substrate having at least one surface with a layer stack formed thereon, the layer stack including a perpendicular recording layer containing a plurality of columnar-shaped magnetic grains extending perpendicularly to the substrate surface for a length, with a first end distal the surface and a second end proximal the surface, wherein each of the magnetic grains has: (1) a gradient of perpendicular magnetic anisotropy field Hk extending along its length between the first end and second ends; and (2) predetermined local exchange coupling strengths along the length.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: November 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Shaoping Li, Kaizhong Gao, Lei Wang, Wenzhong Zhu, Xiaobin Wang
  • Patent number: 8049315
    Abstract: A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: November 1, 2011
    Assignee: Alpha & Omega Semiconductors, Ltd.
    Inventors: Jun Lu, Anup Bhalla, Xiaobin Wang, Allen Chang, Kenny Man Sheng Hu, Xiaotian Zhang
  • Patent number: 8045370
    Abstract: A magnetic tunnel junction memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a magnetic tunnel junction memory unit includes applying a first read current through a magnetic tunnel junction data cell to form a first bit line read voltage, then applying a first magnetic field through the magnetic tunnel junction data cell forming a magnetic field modified magnetic tunnel junction data cell, and then applying a second read current thorough the magnetic field modified magnetic tunnel junction data cell to form a second bit line read voltage. The first read current being less than the second read current. Then comparing the first bit line read voltage with the second bit line read voltage to determine whether the magnetic tunnel junction data cell was in a high resistance state or a low resistance state. Methods of applying a magnetic field to the MTJ and then writing the desired resistance state are also disclosed.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: October 25, 2011
    Assignee: Seagate Technology LLC
    Inventors: Wenzhong Zhu, Yiran Chen, Dimitar V. Dimitrov, Xiaobin Wang
  • Publication number: 20110233667
    Abstract: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.
    Type: Application
    Filed: May 18, 2010
    Publication date: September 29, 2011
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Sung-Shan Tai, Sik Lui, Xiaobin Wang
  • Patent number: 8023316
    Abstract: A magnetic tunnel junction having a compensation element is disclosed. The magnetic tunnel junction includes a synthetic antiferromagnetic reference element, and a synthetic antiferromagnetic compensation element having an opposite magnetization moment to a magnetization moment of the synthetic antiferromagnetic reference element. A free magnetic layer is between the synthetic antiferromagnetic reference element and the synthetic antiferromagnetic compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic layer from the synthetic antiferromagnetic reference element. The free magnetic layer includes Co100-X-YFeXBY wherein X is a value being greater than 30 and Y is a value being greater than 15.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: September 20, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Wei Tian, Xiaobin Wang, Xiaohua Lou
  • Publication number: 20110210390
    Abstract: A semiconductor device includes a drain region comprising an epitaxial layer, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, and an active region contact electrode disposed within the active region contact trench. The active region contact trench has a first width associated with a first region that is in proximity to a bottom portion of the body and a second width associated with a second region that is in proximity to a bottom portion of the source. The first width is substantially different from the second width.
    Type: Application
    Filed: April 15, 2011
    Publication date: September 1, 2011
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Anup Bhalla, Xiaobin Wang
  • Publication number: 20110198605
    Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.
    Type: Application
    Filed: February 12, 2010
    Publication date: August 18, 2011
    Inventors: Xiaobin Wang, Anup Bhalla, Hamza Yilmaz, Daniel Ng
  • Publication number: 20110194337
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
    Type: Application
    Filed: April 21, 2011
    Publication date: August 11, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xiaobin Wang, Yong Lu, Haiwen Xi, Yuankai Zheng, Yiran Chen, Harry Hongyue Liu, Dimitar Dimitrov, Wei Tian, Brian Seungwhan Lee
  • Publication number: 20110194334
    Abstract: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.
    Type: Application
    Filed: April 15, 2011
    Publication date: August 11, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xuguang Wang, Yiran Chen, Dimitar V. Dimitrov, Hongyue Liu, Xiaobin Wang
  • Publication number: 20110140194
    Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
    Type: Application
    Filed: February 17, 2011
    Publication date: June 16, 2011
    Inventors: Anup Bhalla, Xiaobin Wang, Moses Ho
  • Publication number: 20110140167
    Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.
    Type: Application
    Filed: February 9, 2011
    Publication date: June 16, 2011
    Applicant: ALPHA & OMEGA SEMICONDUCTOR, INC.
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Publication number: 20110140228
    Abstract: A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Inventors: Xiaobin Wang, Anup Bhalla, Yeeheng Lee
  • Patent number: 7961509
    Abstract: A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. A magnetic field is applied through the free magnetic layer the forming a magnetic field modified magnetic tunnel junction data cell. Then a second read current is applied thorough the magnetic field modified magnetic tunnel junction data cell forming a second bit line read voltage and compared with the first bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. Methods of applying a destabilizing magnetic field to the MTJ and then writing the desired resistance state are also disclosed.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: June 14, 2011
    Assignee: Seagate Technology LLC
    Inventors: Wenzhong Zhu, Yiran Chen, Xiaobin Wang, Zheng Gao, Haiwen Xi, Dimitar V. Dimitrov
  • Publication number: 20110134682
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 9, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
  • Publication number: 20110134688
    Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 9, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Wenzhong Zhu, Yong Lu, Xiaobin Wang, Yiran Chen, Alan Xuguang Wang, Xiaohua Lou, Haiwen Xi
  • Publication number: 20110128778
    Abstract: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 2, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
  • Patent number: 7952139
    Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: May 31, 2011
    Assignee: Alpha & Omega Semiconductor Ltd.
    Inventors: Anup Bhalla, Xiaobin Wang, Moses Ho
  • Patent number: 7952917
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: May 31, 2011
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li