Patents by Inventor Xiaobin Wang

Xiaobin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130292784
    Abstract: An apparatus and method for enhancing data writing and retention to a magnetic memory element, such as in a non-volatile data storage array. In accordance with various embodiments, a programmable memory element has a reference layer and a storage layer. The reference layer is provided with a fixed magnetic orientation. The storage layer is programmed to have a first region with a magnetic orientation antiparallel to said fixed magnetic orientation, and a second region with a magnetic orientation parallel to said fixed magnetic orientation. A thermal assist layer may be incorporated into the memory element to enhance localized heating of the storage layer to aid in the transition of the first region from parallel to antiparallel magnetic orientation during a write operation.
    Type: Application
    Filed: July 3, 2013
    Publication date: November 7, 2013
    Inventors: Haiwen Xi, Yuankai Zheng, Xiaobin Wang, Dimitar V. Dimitrov, Pat J. Ryan
  • Publication number: 20130280870
    Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer, having a body top surface and a body bottom surface; forming a source; forming an active region contact trench that extends through the source and the body into the drain, wherein bottom surface of the active region contact trench is formed to include at least a portion that is shallower than the body bottom surface; and disposing a contact electrode within the active region contact trench.
    Type: Application
    Filed: April 25, 2013
    Publication date: October 24, 2013
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Publication number: 20130265882
    Abstract: The present disclosure discloses a method for indicating port states and a switch. A main panel of the switch is provided with port indicators one-to-one corresponding to physical ports and N channel indicators. The switch further includes a main chip and a control component. The control component is configured to: receive a port state indication signal from the main chip, and parse the port state indication signal to obtain usage state information of each logical port; generate N enable signals, and control at most one enable signal to be valid at any time point; and control the states of the N channel indicators by using the N enable signals sent from the enable signal controlling module, and control the state of each port indicator according to the N enable signals and the usage state information of each logical port.
    Type: Application
    Filed: March 11, 2013
    Publication date: October 10, 2013
    Inventors: Guolang LI, Xiaobin WANG, Xiang ZHOU, Xizhi JIA
  • Patent number: 8553454
    Abstract: Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A write circuit flows a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and concurrently passes a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit further passes a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: October 8, 2013
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
  • Publication number: 20130228857
    Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Yeeheng Lee, Yongping Ding, Xiaobin Wang
  • Patent number: 8526215
    Abstract: The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory cell to form a map of the resistance state resistance values for a plurality of variable resistive memory cells within a memory array. Then a column or row is selected to be a reference column or reference row based on the map of the resistance state resistance value for a plurality of variable resistive memory cells within a memory array, to minimize read operation errors, and forming a variable resistive memory cell memory array.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: September 3, 2013
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Henry Huang, Hongyue Liu
  • Patent number: 8519495
    Abstract: A magnetic memory device includes a first electrode separated from a second electrode by a magnetic tunnel junction. The first electrode provides a write current path along a length of the first electrode. The magnetic tunnel junction includes a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation. The free magnetic layer is spaced from the first electrode a distance of less than 10 nanometers. A current passing along the write current path generates a magnetic field. The magnetic field switches the free magnetic layer magnetization orientation between a high resistance state magnetization orientation and a low resistance state magnetization orientation.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: August 27, 2013
    Assignee: Seagate Technology LLC
    Inventors: Insik Jin, Hongyue Liu, Yong Lu, Xiaobin Wang
  • Patent number: 8508973
    Abstract: A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: August 13, 2013
    Assignee: Seagate Technology LLC
    Inventors: Insik Jin, Xiaobin Wang, Yong Lu, Haiwen Xi
  • Patent number: 8508988
    Abstract: A magnetic tunnel junction having a compsensation element is disclosed. The magnetic tunnel junction includes a reference element, and a compensation element having an opposite magnetization moment to a magnetization moment of the reference element. A free magnetic layer is between the reference element and the compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic layer from the reference element. The free magnetic layer includes Co100-X-YFeXBY wherein X is a value being greater than 30 and Y is a value being greater than 15.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: August 13, 2013
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Wei Tian, Xiaobin Wang, Xiaohua Lou
  • Patent number: 8501330
    Abstract: A perpendicular magnetic recording medium adapted for high recording density and high data recording rate comprises a non-magnetic substrate having at least one surface with a layer stack formed thereon, the layer stack including a perpendicular recording layer containing a plurality of columnar-shaped magnetic grains extending perpendicularly to the substrate surface for a length, with a first end distal the surface and a second end proximal the surface, wherein each of the magnetic grains has: (1) a gradient of perpendicular magnetic anisotropy field Hk extending along its length between the first end and second ends; and (2) predetermined local exchange coupling strengths along the length.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: August 6, 2013
    Assignee: Seagate Technology LLC
    Inventors: Shaoping Li, Kaizhong Gao, Lei Wang, Wenzhong Zhu, Xiaobin Wang
  • Patent number: 8495118
    Abstract: A random number generator device that utilizes a magnetic tunnel junction. An AC current source is in electrical connection to the magnetic tunnel junction to provide an AC current having an amplitude and a frequency through the free layer of the magnetic tunnel junction, the AC current configured to switch the magnetization orientation of the free layer via thermal magnetization. A read circuit is used to determine the relative orientation of the free layer magnetization in relation to the reference layer magnetization orientation.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: July 23, 2013
    Assignee: Seagate Technology LLC
    Inventors: Xiaobin Wang, Wenzhong Zhu, Henry Huang, Yiran Chen, Haiwen Xi
  • Patent number: 8493555
    Abstract: A distributed Brillouin optical fiber sensing system employs a sensing optical fiber that supports two or more (i.e., few) guided modes. Pump light supported by one of the guided modes is used to form a dynamic Brillouin grating (DBG). Probe light supported by at least one of the other guided modes interacts with the DBG to form reflected probe light that is received and analyzed to determine a Brillouin frequency shift and a reflection location, which in turn allows for making a measurement of at least one condition along the sensing optical fiber. Supporting the pump and probe light in different guided modes results in the optical fiber sensing system having a higher spatial resolution than sensing systems where the pump light and probe light share a common guided mode.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: July 23, 2013
    Assignee: Corning Incorporated
    Inventors: Ming-Jun Li, Shenping Li, Xiaobin Wang
  • Patent number: 8493556
    Abstract: Some embodiments of a distributed Brillouin optical fiber sensing system employs a sensing optical fiber that supports two or more (i.e., few) guided modes. Pump light supported by one of the guided modes is used to form a dynamic Brillouin grating (DBG). Probe light supported by at least one of the other guided modes interacts with the DBG to form reflected probe light that is received and analyzed to determine a Brillouin frequency shift, a phase matching wavelength between probe and pump light, a reflection location, which in turn allows for making a measurement of at least one condition along the sensing optical fiber. Supporting the pump and probe light in different guided modes results in the optical fiber sensing system being able to simultaneously measure temperature and strain and having a higher spatial resolution than sensing systems where the pump light and probe light share a common guided mode.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: July 23, 2013
    Assignee: Corning Incorporated
    Inventors: Ming-Jun Li, Shenping Li, Xiaobin Wang
  • Publication number: 20130175612
    Abstract: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.
    Type: Application
    Filed: February 28, 2013
    Publication date: July 11, 2013
    Inventors: Sung-Shan Tai, Sik Lui, Xiaobin Wang
  • Patent number: 8481181
    Abstract: Approaches to reduce switching field distribution in energy assisted magnetic storage devices involve first and second exchange coupled magnetic elements. The first magnetic elements have anisotropy, Hk1, volume, V1 and the second magnetic elements are magnetically exchange coupled to the first magnetic elements and have anisotropy Hk2, and volume V2. The thermal stability of the exchange coupled magnetic elements is greater than about 60 kBT at a storage temperature of about 300 K. The magnetic switching field distribution, SFD, of the exchange coupled magnetic elements is less than about 200% at a predetermined magnetic switching field and a predetermined assisting switching energy.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: July 9, 2013
    Assignee: Seagate Technology LLC
    Inventors: Xiaobin Wang, Kaizhong Gao
  • Patent number: 8482971
    Abstract: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: July 9, 2013
    Assignee: Seagate Technology LLC
    Inventors: Xuguang Wang, Yiran Chen, Dimitar V. Dimitrov, Hongyue Liu, Xiaobin Wang
  • Patent number: 8482967
    Abstract: An apparatus and method for enhancing data writing and retention to a magnetic memory element, such as in a non-volatile data storage array. In accordance with various embodiments, a programmable memory element has a reference layer and a storage layer. The reference layer is provided with a fixed magnetic orientation. The storage layer is programmed to have a first region with a magnetic orientation antiparallel to said fixed magnetic orientation, and a second region with a magnetic orientation parallel to said fixed magnetic orientation. A thermal assist layer may be incorporated into the memory element to enhance localized heating of the storage layer to aid in the transition of the first region from parallel to antiparallel magnetic orientation during a write operation.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: July 9, 2013
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Yuankai Zheng, Xiaobin Wang, Dimitar V. Dimitrov, Pat J. Ryan
  • Patent number: 8471332
    Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: June 25, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Xiaobin Wang, Moses Ho
  • Patent number: 8450794
    Abstract: A semiconductor device is formed on a semiconductor substrate. The device comprises a drain; an epitaxial layer overlaying the drain; a body disposed in the epitaxial layer, having a body top surface and a body bottom surface; a source embedded in the body, extending from the body top surface into the body; a first gate trench extending into the epitaxial layer; a first gate disposed in the first gate trench; an active region contact trench extending through the source and at least part of the body into the drain; an active region contact electrode disposed within the active region contact trench; a second gate trench extending into the epitaxial layer; a second gate disposed in the gate trench; a gate contact trench formed within the second gate; and a gate contact electrode disposed within the gate contact trench.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: May 28, 2013
    Assignee: Alpha & Omega Semiconductor Limited
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Patent number: 8400825
    Abstract: Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a current through the magnetic tunnel junction cell, the spin torque current source having a direction perpendicular to the magnetization orientations, and also includes a magnetic ampere field current source is oriented in a direction orthogonal or at some angles to the magnetization orientations.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: March 19, 2013
    Assignee: Seagate Technologies LLC
    Inventors: Xiaobin Wang, Haiwen Xi, Hongyue Liu, Insik Jin, Andreas Roelofs, Eileen Yan, Dimitar V. Dimitrov