Patents by Inventor Xiaobin Wang

Xiaobin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7948029
    Abstract: A semiconductor device includes a drain, an epitaxial layer overlaying the drain, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, the active region contact trench having a varying contact trench depth, and an active region contact electrode disposed within the active region contact trench.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: May 24, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Xiaobin Wang
  • Publication number: 20110116303
    Abstract: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.
    Type: Application
    Filed: January 24, 2011
    Publication date: May 19, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xiaobin Wang, Yiran Chen, Alan Wang, Haiwen Xi, Wenzhong Zhu, Hai Li, Hongyue Liu
  • Patent number: 7944742
    Abstract: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: May 17, 2011
    Assignee: Seagate Technology LLC
    Inventors: Xuguang Wang, Yiran Chen, Dimitar V. Dimitrov, Hongyue Liu, Xiaobin Wang
  • Patent number: 7944730
    Abstract: A method of writing to a resistive sense memory unit includes applying a first voltage across a resistive sense memory cell and a semiconductor transistor to write a first data state to the resistive sense memory cell. The first voltage forms a first write current for a first time duration through the resistive sense memory cell in a first direction. Then the method includes applying a second voltage across the resistive sense memory cell and the transistor to write a second data state to the resistive sense memory cell. The second voltage forms a second write current for a second duration through the resistive sense memory cell in a second direction. The second direction opposes the first direction, the first voltage has a different value than the second voltage, and the first duration is substantially the same as the second duration.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: May 17, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Wengzhong Zhu, Xiaobin Wang, Ran Wang, Hongyue Liu
  • Publication number: 20110108998
    Abstract: A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.
    Type: Application
    Filed: January 14, 2011
    Publication date: May 12, 2011
    Applicant: ALPHA & OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Jun Lu, Anup Bhalla, Xiaobin Wang, Allen Chang, Man Sheng Hu, Xiaotian Zhang
  • Patent number: 7940551
    Abstract: Spin-transfer torque memory having a specular insulative spacer is disclosed. The spin-transfer torque memory unit includes a free magnetic layer, a reference magnetic layer, an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the reference magnetic layer, an electrode layer, and an electrically insulating and electronically reflective layer separating the electrode layer and the free magnetic layer.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: May 10, 2011
    Assignee: Seagate Technology, LLC
    Inventors: Yuankai Zheng, Dimitar V. Dimitrov, Wei Tian, Dexin Wang, Zheng Gao, Xiaobin Wang
  • Patent number: 7936592
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Xiaobin Wang, Yong Lu, Haiwen Xi, Yuankai Zheng, Yiran Chen, Harry Hongyue Liu, Dimitar Dimitrov, Wei Tan, Brian Seungwhan Lee
  • Publication number: 20110085373
    Abstract: Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to.
    Type: Application
    Filed: December 15, 2010
    Publication date: April 14, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yuankai Zheng, Yiran Chen, Xiaobin Wang, Zheng Gao, Dimitar V. Dimitrov, Wenzhong Zhu, Yong Lu
  • Publication number: 20110080769
    Abstract: The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory cell to form a map of the resistance state resistance values for a plurality of variable resistive memory cells within a memory array. Then a column or row is selected to be a reference column or reference row based on the map of the resistance state resistance value for a plurality of variable resistive memory cells within a memory array, to minimize read operation errors, and forming a variable resistive memory cell memory array.
    Type: Application
    Filed: December 15, 2010
    Publication date: April 7, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Henry Huang, Hongyue Liu
  • Publication number: 20110075471
    Abstract: An apparatus and method for enhancing read and write sense margin in a memory cell having a resistive sense element (RSE), such as but not limited to a resistive random access memory (RRAM) element or a spin-torque transfer random access memory (STRAM) element. The RSE has a hard programming direction and an easy programming direction. A write current is applied in either the hard programming direction or the easy programming direction to set the RSE to a selected programmed state. A read circuit subsequently passes a read sense current through the cell in the hard programming direction to sense the selected programmed state of the cell.
    Type: Application
    Filed: December 6, 2010
    Publication date: March 31, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Wenzhong Zhu, Hai Li, Yiran Chen, Xiaobin Wang, Henry Huang, Haiwen Xi
  • Publication number: 20110076815
    Abstract: A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
    Type: Application
    Filed: October 29, 2010
    Publication date: March 31, 2011
    Inventors: Anup Bhalla, Xiaobin Wang, Wei Wang, Yi Su, Daniel Ng
  • Publication number: 20110076516
    Abstract: A perpendicular magnetic recording medium adapted for high recording density and high data recording rate comprises a non-magnetic substrate having at least one surface with a layer stack formed thereon, the layer stack including a perpendicular recording layer containing a plurality of columnar-shaped magnetic grains extending perpendicularly to the substrate surface for a length, with a first end distal the surface and a second end proximal the surface, wherein each of the magnetic grains has: (1) a gradient of perpendicular magnetic anisotropy field Hk extending along its length between the first end and second ends; and (2) predetermined local exchange coupling strengths along the length.
    Type: Application
    Filed: December 7, 2010
    Publication date: March 31, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Shaoping Li, Kaizhong Gao, Lei Wang, Wenzhong Zhu, Xiaobin Wang
  • Patent number: 7916528
    Abstract: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: March 29, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
  • Patent number: 7910486
    Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: March 22, 2011
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Publication number: 20110058405
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.
    Type: Application
    Filed: November 15, 2010
    Publication date: March 10, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Ran Wang, Harry Hongyue Liu
  • Publication number: 20110049658
    Abstract: Magnetic tunnel junctions having a specular insulative spacer are disclosed. The magnetic tunnel junction includes a free magnetic layer, a reference magnetic layer, an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the reference magnetic layer, and an electrically insulating and electronically reflective layer positioned to reflect at least a portion of electrons back into the free magnetic layer.
    Type: Application
    Filed: November 11, 2010
    Publication date: March 3, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yuankai Zheng, Dimitar V. Dimitrov, Wei Tian, Dexin Wang, Zheng Gao, Xiaobin Wang
  • Patent number: 7898838
    Abstract: Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: March 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Henry Huang, Hongyue Liu
  • Patent number: 7898844
    Abstract: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: March 1, 2011
    Assignee: Seagate Technology, LLC
    Inventors: Xiaobin Wang, Yiran Chen, Alan Wang, Haiwen Xi, Wenzhong Zhu, Hai Li, Hongyue Liu
  • Patent number: 7894250
    Abstract: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: February 22, 2011
    Assignee: Seagate Technology LLC
    Inventors: Alan Xuguang Wang, Xiaobin Wang, Dimitar V. Dimitrov, Hai Li, Haiwen Xi, Harry Hongyue Liu
  • Patent number: 7884454
    Abstract: A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: February 8, 2011
    Assignee: Alpha & Omega Semiconductor, Ltd
    Inventors: Jun Lu, Anup Bhalla, Xiaobin Wang, Allen Chang, Man Sheng Hu, Xiaotian Zhang