Abstract: An apparatus and method for enhancing read and write sense margin in a memory cell having a resistive sense element (RSE), such as but not limited to a resistive random access memory (RRAM) element or a spin-torque transfer random access memory (STRAM) element. The RSE has a hard programming direction and an easy programming direction. A write current is applied in either the hard programming direction or the easy programming direction to set the RSE to a selected programmed state. A read circuit subsequently passes a read sense current through the cell in the hard programming direction to sense the selected programmed state of the cell.

Abstract: A multi-bit spin torque magnetic element that has a ferromagnetic pinned layer having a pinned magnetization orientation, a non-magnetic layer, and a ferromagnetic free layer having a magnetization orientation switchable among at least four directions, the at least four directions being defined by a physical shape of the free layer. The magnetic element has at least four distinct resistance states. Magnetic elements with at least eight magnetization directions are also provided.

Abstract: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.

Abstract: Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to.

Abstract: The present invention features a field effect transistor that includes a semiconductor substrate having gate, source and drain regions; and a p-n junction formed on the semiconductor substrate and in electrical communication with the gate, drain and source regions to establish a desired breakdown voltage. In one embodiment, gate region further includes a plurality of spaced-apart trench gates with the p-n junction being defined by an interface between an epitaxial layer in which the trench gates are formed and the interface with a metallization layer. The breakdown voltage provided is defined, in part by the number of p-n junctions formed. In another embodiment, the p-n junctions are formed by generating a plurality of spaced-apart p-type regions in areas of the epitaxial layer located adjacent to the trench gates.

Abstract: A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer.

Abstract: An apparatus and method for enhancing data writing and retention to a magnetic memory element, such as in a non-volatile data storage array. In accordance with various embodiments, a programmable memory element has a reference layer and a storage layer. The reference layer is provided with a fixed magnetic orientation. The storage layer is programmed to have a first region with a magnetic orientation antiparallel to said fixed magnetic orientation, and a second region with a magnetic orientation parallel to said fixed magnetic orientation. A thermal assist layer may be incorporated into the memory element to enhance localized heating of the storage layer to aid in the transition of the first region from parallel to antiparallel magnetic orientation during a write operation.

Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.

Abstract: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.

Abstract: A semiconductor device is formed on a semiconductor substrate. The device comprises a drain; an epitaxial layer overlaying the drain; a body disposed in the epitaxial layer, having a body top surface and a body bottom surface; a source embedded in the body, extending from the body top surface into the body; a first gate trench extending into the epitaxial layer; a first gate disposed in the first gate trench; an active region contact trench extending through the source and at least part of the body into the drain; an active region contact electrode disposed within the active region contact trench; a second gate trench extending into the epitaxial layer; a second gate disposed in the gate trench; a gate contact trench formed within the second gate; and a gate contact electrode disposed within the gate contact trench.

Abstract: The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory cell to form a map of the resistance state resistance values for a plurality of variable resistive memory cells within a memory array. Then a column or row is selected to be a reference column or reference row based on the map of the resistance state resistance value for a plurality of variable resistive memory cells within a memory array, to minimize read operation errors, and forming a variable resistive memory cell memory array.

Abstract: A perpendicular magnetic recording medium adapted for high recording density and high data recording rate comprises a non-magnetic substrate having at least one surface with a layer stack formed thereon, the layer stack including a perpendicular recording layer containing a plurality of columnar-shaped magnetic grains extending perpendicularly to the substrate surface for a length, with a first end distal the surface and a second end proximal the surface, wherein each of the magnetic grains has: (1) a gradient of perpendicular magnetic anisotropy field Hk extending along its length between the first end and second ends; and (2) predetermined local exchange coupling strengths along the length.

Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.

Abstract: Magnetic shift registers in which data writing and reading is accomplished by moving the magnetic domain walls by electric current. Various embodiments of domain wall nodes or anchors that stabilize a domain wall are provided. In some embodiments, the wall anchors are elements separate from the magnetic track. In other embodiments, the wall anchors are disturbances in the physical configuration of the magnetic track. In still other embodiments, the wall anchors are disturbances in the material of the magnetic track.

Abstract: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.

Abstract: A semiconductor device is formed on a semiconductor substrate. The device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface and a body bottom surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and at least part of the body into the drain, wherein the active region contact trench is shallower than the body bottom surface, and an active region contact electrode disposed within the active region contact trench.

Abstract: A magnetic tunnel junction having a compsensation element is disclosed. The magnetic tunnel junction includes a reference element, and a compensation element having an opposite magnetization moment to a magnetization moment of the reference element. A free magnetic layer is between the reference element and the compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic layer from the reference element. The free magnetic layer includes Co100-X-YFeXBY wherein X is a value being greater than 30 and Y is a value being greater than 15.

Abstract: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.

Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.