Abstract: The invention relates to methods for providing information for use by a navigation satellite system (NSS) receiver and/or processing entity receiving data therefrom, for positioning purposes. In one embodiment, satellite orbit information and satellite clock error information applicable over a wide area and to epoch t1 is obtained (s10) for each of a plurality of NSS satellites. Ambiguities in the carrier phase of NSS signals received at epoch t1 at narrow area reference stations are estimated (s20). For each satellite, the satellite orbit and satellite clock error at epoch t2 are predicted (s30). A residual error for modelling errors having a common or substantially common line-of-sight dependency is estimated (s40a). The residual error is added (s50a) to the predicted satellite clock error to form a redefined satellite clock error. The invention also relates to variants of the above-mentioned method, and to systems, computer programs, and computer program products.

Abstract: A method for determining a performance indicator is performed by an electronic device. The method includes: obtaining a first test result by testing preset indicators of a repeated Open Cable system in a first test environment, and obtaining a second test result by testing the preset indicators of the repeated Open Cable system in a second test environment, in which the preset indicators include a quality factor Q value and a linear signal noise ratio (SNR); determining an external SNR value of the system based on the first test result and the second test result; and determining an intrinsic SNR value of the system based on the external SNR value, the linear SNR, a nonlinear SNR, and a guided acousto-optic wave Brillouin scattering (GAWBS) SNR.

Abstract: One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

Abstract: An adapter terminal includes a fixing portion, a first mating portion and a second mating portion. The first mating portion is connected to the fixing portion. The first mating portion is configured to mate with a conductive terminal of a connector. The first mating portion includes a first base portion and a first elastic piece portion at least partially protruding beyond the first base portion. The second mating portion is connected to the fixing portion. The second mating portion is configured to mate with a conductive terminal of a mating connector. The second mating portion includes a second base portion and a second elastic piece portion at least partially protruding beyond the second base portion. The adapter terminal disclosed in the present disclosure has simple structure and low cost. Besides, a connector and a connector assembly having the adapter terminal are also disclosed.

Abstract: A connector assembly includes a connector and a locking structure. The connector includes an insulating body. The insulating body includes at least one mating end portion. The mating end portion defines a first mating space for receiving a conductive terminal. The locking structure is held to the mating end portion. The locking structure has a pre-locking position and a locking position relative to the mating end portion. The locking structure includes a body portion and a resisting portion. The body portion is configured to receive a high voltage interlock terminal. The resisting portion is configured such that when the locking structure is at the pre-tightened position, the resisting portion is located outside the first mating space; when the locking structure is at the locking position, at least part of the resisting portion protrudes into the first mating space.

Abstract: One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

Abstract: The present disclosure provides an actively encapsulated liposome nanocarrier delivery system. The liposome nanocarrier delivery system includes a liposome carrier and substances actively encapsulated thereby for use in preventing and/or treating atherosclerosis or diseases related to atherosclerosis. The preparation of the nanocarrier delivery system includes the step of adding a saline solution that causes an acidity gradient of a liposome solution inside and outside of a body so as to hydrate the substances actively encapsulated by the liposome carrier for use in preventing and/or treating atherosclerosis or diseases related to atherosclerosis. Further provided are a preparation method for the liposome nanocarrier delivery system and an application thereof.

Abstract: One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread architecture, the general-purpose graphics compute unit to concurrently execute the first instruction and the second instruction.

Abstract: Some embodiments of the invention pertain to generating (s10) and providing (s20) ionospheric disturbance information from navigation satellite system (NSS) reference stations or reference station system to NSS receivers or NSS receiver systems. Station-specific and/or satellite-specific ionospheric disturbance information may be obtained (s40) on the receiver side for mitigation purposes (s60, s70, s80) in the context of estimating parameters useful to determine a position. The ionospheric disturbance information may for example comprise ionospheric amplitude scintillation information, ionospheric phase scintillation information, and/or ionospheric delay gradient information. Systems, vehicles, and computer programs are also disclosed.

Abstract: Some embodiments of the invention pertain to generating (s10) and providing (s20) ionospheric disturbance information from navigation satellite system (NSS) reference stations or reference station system to NSS receivers or NSS receiver systems. Station-specific and/or satellite-specific ionospheric disturbance information may be obtained (s40) on the receiver side for mitigation purposes (s60, s70, s80) in the context of estimating parameters useful to determine a position. The ionospheric disturbance information may for example comprise ionospheric amplitude scintillation information, ionospheric phase scintillation information, and/or ionospheric delay gradient information. Systems, vehicles, and computer programs are also disclosed.

Abstract: One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point operations that are configurable to include two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions. The floating-point operations may include a first operation at a first precision and a second operation at a second precision. The first operation may include a multiply having at least one 16-bit floating-point input and the second operation may include an accumulate having a 32-bit floating-point input.

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

Abstract: A rapid and automatic virus imaging and analysis system includes (i) electron optical sub-systems (EOSs), each of which has a large field of view (FOV) and is capable of instant magnification switching for rapidly scanning a virus sample; (ii) sample management sub-systems (SMSs), each of which automatically loads virus samples into one of the EOSs for virus sample scanning and then unloads the virus samples from the EOS after the virus sample scanning is completed; (iii) virus detection and classification sub-systems (VDCSs), each of which automatically detects and classifies a virus based on images from the EOS virus sample scanning; and (iv) a cloud-based collaboration sub-system for analyzing the virus sample scanning images, storing images from the EOS virus sample scanning, and storing and analyzing machine data associated with the EOSs, the SMSs, and the VDCSs.

Abstract: The present disclosure discloses a display panel. The display panel includes a lighting test unit. The lighting test unit includes: signal input terminal sets, each including signal input terminals; shorting bar sets, each including shorting bars; and data signal line sets, each including data signal lines, where the signal input terminals are electrically connected to the shorting bars, the data signal lines are electrically connected to the shorting bars, and each shorting bar is connected end to end.

Abstract: A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

Abstract: The present application belongs to the field of compounds, and particularly relates to the perovskite-type compound ABX3. As a finding of the present application, the structural characteristics of the perovskite type enables the type of compound to be highly stable, thus overcoming the unsafety of an explosive having poor stability in the prior art. Meanwhile, the structural characteristics of the compound, such as rich energetic ligands, as well as the alternately arranged oxidizing energetic anions and reducing organic cations in the space, endow the compound with excellent performance on instantaneously releasing energy at detonation. The resulting three-dimensional structure allows the compound to not only have an energetic material effect but also overcome shortcomings of some existing energetic materials.

Abstract: One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.