Patents by Inventor Xiaoming Chen

Xiaoming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11727246
    Abstract: Embodiments provide systems and methods which facilitate optimization of a convolutional neural network (CNN). One embodiment provides for a non-transitory machine-readable medium storing instructions that cause one or more processors to perform operations comprising processing a trained convolutional neural network (CNN) to generate a processed CNN, the trained CNN having weights in a floating-point format. Processing the trained CNN includes quantizing the weights in the floating-point format to generate weights in an integer format. Quantizing the weights includes generating a quantization table to enable non-uniform quantization of the weights and quantizing the weights from the floating-point format to the integer format using the quantization table. The operations additionally comprise performing an inference operation utilizing the processed CNN with the integer format weights.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Liwei Ma, Elmoustapha Ould-Ahmed-Vall, Barath Lakshmanan, Ben J. Ashbaugh, Jingyi Jin, Jeremy Bottleson, Mike B. Macpherson, Kevin Nealis, Dhawal Srivastava, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman, Altug Koker, Abhishek R. Appu
  • Patent number: 11720355
    Abstract: One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Publication number: 20230244112
    Abstract: The present disclosure discloses a display panel. The display panel includes a lighting test unit. The lighting test unit includes: signal input terminal sets, each including signal input terminals; shorting bar sets, each including shorting bars; and data signal line sets, each including data signal lines, where the signal input terminals are electrically connected to the shorting bars, the data signal lines are electrically connected to the shorting bars, and each shorting bar is connected end to end.
    Type: Application
    Filed: August 10, 2021
    Publication date: August 3, 2023
    Inventors: Xiaoming CHEN, Peng WAN
  • Patent number: 11693658
    Abstract: One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a ternary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the ternary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: July 4, 2023
    Assignee: Intel Corporation
    Inventors: Kevin Nealis, Anbang Yao, Xiaoming Chen, Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha
  • Patent number: 11682817
    Abstract: A W-band E-plane waveguide bandpass filter includes a rectangular waveguide configured to feed a W-band signal, and a dielectric substrate. The dielectric substrate is inserted into the center of the waveguide. The dielectric substrate is provided with a spoof surface plasmon polariton (SSPP) array configured to transmit a TM-mode surface wave to achieve the bandpass filtering response.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: June 20, 2023
    Assignee: Xi'an Jiaotong University
    Inventors: Kaida Xu, Yiqun Liu, Xiaoming Chen, Jianxing Li, Anxue Zhang
  • Patent number: 11668841
    Abstract: Methods and apparatus for processing of GNSS signals are presented. These include GNSS processing with obtaining GNSS data derived from signals received at a rover antenna, obtaining correction data, maintaining a time sequence of at least one rover position and at least one rover position difference with associated time tags, using the time sequence to determine at least one derived rover position by, starting from a position determined using corrections synchronous with rover data as an anchor position at a time tag, deriving a new anchor position for the time tag of the anchor position and at least one other estimated rover position at the time tag of the anchor position, and/or reporting the new anchor position and/or a new derived rover position.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: June 6, 2023
    Assignee: Trimble Inc.
    Inventors: Ulrich Vollath, Nicholas Charles Talbot, Markus Glocker, Xiaoming Chen, Rodrigo Leandro
  • Publication number: 20230170178
    Abstract: A rapid and automatic virus imaging and analysis system includes (i) electron optical sub-systems (EOSs), each of which has a large field of view (FOV) and is capable of instant magnification switching for rapidly scanning a virus sample; (ii) sample management sub-systems (SMSs), each of which automatically loads virus samples into one of the EOSs for virus sample scanning and then unloads the virus samples from the EOS after the virus sample scanning is completed; (iii) virus detection and classification sub-systems (VDCSs), each of which automatically detects and classifies a virus based on images from the EOS virus sample scanning; and (iv) a cloud-based collaboration sub-system for analyzing the virus sample scanning images, storing images from the EOS virus sample scanning, and storing and analyzing machine data associated with the EOSs, the SMSs, and the VDCSs.
    Type: Application
    Filed: January 24, 2023
    Publication date: June 1, 2023
    Applicant: BORRIES PTE. LTD.
    Inventors: Zhongwei Chen, Xiaoming Chen, Daniel Tang, Liang-Fu Fan
  • Publication number: 20230170597
    Abstract: A W-band E-plane waveguide bandpass filter includes a rectangular waveguide configured to feed a W-band signal, and a dielectric substrate. The dielectric substrate is inserted into the center of the waveguide. The dielectric substrate is provided with a spoof surface plasmon polariton (SSPP) array configured to transmit a TM-mode surface wave to achieve the bandpass filtering response.
    Type: Application
    Filed: September 6, 2022
    Publication date: June 1, 2023
    Inventors: Kaida XU, Yiqun LIU, Xiaoming CHEN, Jianxing LI, Anxue ZHANG
  • Patent number: 11664189
    Abstract: The present invention provides an apparatus of charged-particle beam e.g. an electron microscope comprising a plasma generator for selectively cleaning BSE detector. In various embodiments, the plasma generator is located between a sample stage and a sample table having one or more openings or holes. The plasma generator generates plasma and distributes or dissipates the plasma through the openings of the sample table toward and onto surface of the BSE detector. Cleaning contaminants on the surface of the BSE detector frequently and selectively with in-situ generated plasma can prevent the detectors from performance deterioration such as losing resolution and contrast in imaging at high levels of magnification.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: May 30, 2023
    Assignee: BORRIES PTE. LTD.
    Inventors: Zhongwei Chen, Xiaoming Chen, Daniel Tang, Liang-Fu Fan
  • Patent number: 11664186
    Abstract: The present invention provides an apparatus of electron beam comprising an electron gun with a pinnacle limiting plate having at least one current-limiting aperture. The pinnacle limiting plate is located between a bottom (or lowest) anode and a top (or highest) condenser within the electron gun. A current (ampere) of the electron beam that has passed through the current-limiting aperture remains the same (unchanged) after the electron beam travels through the top condenser and an electron optical column and arrives at a sample space. Electron-electron interaction of the electron beam is thus reduced.
    Type: Grant
    Filed: August 7, 2022
    Date of Patent: May 30, 2023
    Assignee: BORRIES PTE. LTD.
    Inventors: Zhongwei Chen, Wei Fang, Xiaoming Chen, Daniel Tang, Liang-Fu Fan
  • Publication number: 20230099165
    Abstract: Aqueous hydrocortisone sodium phosphate and monothioglycerol formulations are disclosed.
    Type: Application
    Filed: November 18, 2022
    Publication date: March 30, 2023
    Applicant: ANTARES PHARMA, INC.
    Inventors: Xiaoming CHEN, Shaowei ONG
  • Publication number: 20230092978
    Abstract: This disclosure provides a resource tapping method, a resource tapping apparatus and an electronic device, and relates to the field of computer technology, in particular to the technical field of artificial intelligence, such as deep learning and machine learning. A specific implementation is as follows: obtaining operation data in M resource dimensions of a target cabinet, the M resource dimensions including a power resource, where M is a positive integer; determining a target power over-allocation value of the target cabinet based on the operation data, the target power over-allocation value being used for indicating an allowable power increment on the basis of a power rating of the target cabinet; and determining, based on the target power over-allocation value, a first quantity of additional servers deployable in the target cabinet.
    Type: Application
    Filed: November 22, 2022
    Publication date: March 23, 2023
    Inventors: Xiaoming CHEN, Yongfeng JI, Zhe LI
  • Patent number: 11599798
    Abstract: A method operating a Graphics Processing Unit (GPU) memory can be provided by accessing specified training parameters used to train a Deep Neural Network (DNN) using a GPU with a local GPU memory, the specified training parameters including at least a specified batch size of samples configured to train the DNN. A sub-batch size of the samples can be defined that is less than or equal to the specified batch size of samples in response to determining that an available size of the local GPU memory is insufficient to store all data associated with training the DNN using one batch of the samples. Instructions configured to train the DNN using the sub-batch size can be defined so that an accuracy of the DNN trained using the sub-batch size is about equal to an accuracy of the DNN trained using the specified batch size of the samples.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: March 7, 2023
    Assignee: UNIVERSITY OF NOTRE DAME DU LAC
    Inventors: Xiaobo Sharon Hu, Danny Ziyi Chen, Xiaoming Chen
  • Publication number: 20230061331
    Abstract: One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point operations that are configurable to include two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions. The floating-point operations may include a first operation at a first precision and a second operation at a second precision. The first operation may include a multiply having at least one 16-bit floating-point input and the second operation may include an accumulate having a 32-bit floating-point input.
    Type: Application
    Filed: October 5, 2022
    Publication date: March 2, 2023
    Applicant: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland
  • Publication number: 20230061670
    Abstract: One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.
    Type: Application
    Filed: November 1, 2022
    Publication date: March 2, 2023
    Applicant: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland
  • Patent number: 11593938
    Abstract: A rapid and automatic virus imaging and analysis system includes (i) electron optical sub-systems (EOSs), each of which has a large field of view (FOV) and is capable of instant magnification switching for rapidly scanning a virus sample; (ii) sample management sub-systems (SMSs), each of which automatically loads virus samples into one of the EOSs for virus sample scanning and then unloads the virus samples from the EOS after the virus sample scanning is completed; (iii) virus detection and classification sub-systems (VDCSs), each of which automatically detects and classifies a virus based on images from the EOS virus sample scanning; and (iv) a cloud-based collaboration sub-system for analyzing the virus sample scanning images, storing images from the EOS virus sample scanning, and storing and analyzing machine data associated with the EOSs, the SMSs, and the VDCSs.
    Type: Grant
    Filed: October 31, 2021
    Date of Patent: February 28, 2023
    Assignee: BORRIRS PTE. LTD.
    Inventors: Zhongwei Chen, Xiaoming Chen, Daniel Tang, Liang-Fu Fan
  • Publication number: 20230046506
    Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.
    Type: Application
    Filed: October 17, 2022
    Publication date: February 16, 2023
    Applicant: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Patent number: 11580361
    Abstract: An apparatus to facilitate neural network (NN) training is disclosed. The apparatus includes training logic to receive one or more network constraints and train the NN by automatically determining a best network layout and parameters based on the network constraints.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Gokcen Cilingir, Elmoustapha Ould-Ahmed-Vall, Rajkishore Barik, Kevin Nealis, Xiaoming Chen, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Abhishek Appu, John C. Weast, Sara S. Baghsorkhi, Barnan Das, Narayan Biswal, Stanley J. Baran, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • Publication number: 20230039729
    Abstract: Methods and apparatus relating to autonomous vehicle neural network optimization techniques are described. In an embodiment, the difference between a first training dataset to be used for a neural network and a second training dataset to be used for the neural network is detected. The second training dataset is authenticated in response to the detection of the difference. The neural network is used to assist in an autonomous vehicle/driving. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: October 11, 2022
    Publication date: February 9, 2023
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. MacPherson, John C. Weast, Justin E. Gottschlich, Jingyi Jin, Barath Lakshmanan, Chandrasekaran Sakthivel, Michael S. Strickland, Joydeep Ray, Kamal Sinha, Prasoonkumar Surti, Balaji Vembu, Ping T. Tang, Anbang Yao, Tatiana Shpeisman, Xiaoming Chen
  • Patent number: D987424
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: May 30, 2023
    Assignee: Penn Engineering & Manufacturing Corp.
    Inventors: Jonathan Brunk, XiaoMing Chen