Abstract: Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple or mixed precisions and dynamic ranges.

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The streaming multiprocessor comprises multiple processing blocks including multiple processing cores. The processing cores include independent integer and floating-point data paths that are configurable to concurrently execute multiple independent instructions. A memory is coupled with the multiple processing blocks.

Abstract: Some embodiments of the invention relate to methods carried out by an NSS receiver and/or a processing entity capable of receiving data therefrom, for estimating parameters derived from NSS signals useful to determine a position, and for generating protection level(s) for an application relying on NSS observations to produce an estimate of said parameters. A float solution is computed using NSS signals observed by the NSS receiver. A best integer ambiguity combination that minimizes an error norm is identified based on the float solution. Additional integer ambiguity combinations are identified, which have the smallest error norms that, together with the error norm of the best integer ambiguity combination, jointly satisfy the integrity risk. A measure of spread of the best and additional integer ambiguity combinations is computed. The protection level(s) is then generated from the measure of spread. Systems and computer programs are also disclosed.

Abstract: The present invention provides an apparatus of charged-particle beam e.g. an electron microscope comprising a plasma generator for selectively cleaning BSE detector. In various embodiments, the plasma generator is located between a sample stage and a sample table having one or more openings or holes. The plasma generator generates plasma and distributes or dissipates the plasma through the openings of the sample table toward and onto surface of the BSE detector. Cleaning contaminants on the surface of the BSE detector frequently and selectively with in-situ generated plasma can prevent the detectors from performance deterioration such as losing resolution and contrast in imaging at high levels of magnification.

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

Abstract: A nano-micelle preparation of icaritin. The preparation comprises icaritin and polymer auxiliary materials. Further provided is a preparation method for the nano-micelle preparation, and the prepared nano-micelle preparation of icaritin has the advantage of high bioavailability.

Abstract: A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

Abstract: A process for cleaning particulate matter from the interior of a muffle of an optical fiber draw furnace includes propagating sound waves through the interior of the muffle at a frequency of from about 75 Hz to about 5000 Hz and an intensity of from about 110 dB to about 160 dB.

Abstract: One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread (SIMT) architecture, the general-purpose graphics compute unit to simultaneously execute the first instruction and the second instruction, wherein the integer operation corresponds to a memory address calculation.

Abstract: Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple or mixed precisions and dynamic ranges.

Abstract: Certain aspects of the present disclosure generally relate to a circuit board with ground vias offset from associated ground bumps. One example circuit board generally includes a first signal connection terminal configured to connect a signal line of the circuit board to an integrated circuit (IC); a ground plane having a first ground connection terminal disposed adjacent to the first signal connection terminal, the first ground connection terminal being configured to provide a ground connection between the ground plane and the IC; and a first ground via associated with and disposed adjacent to the first ground connection terminal and coupled to the ground plane, wherein, from an overhead view of the circuit board, the first ground via is located at a position that is offset from a first axis on which the first signal connection terminal and the first ground connection terminal are disposed.

Abstract: A lookup-table type TL-TCAM hardware search engine includes a SL decoder, a TL-TCAM array, and the data stored in the TL-TCAM hardware search engine is obtained by performing lookup table operation in the corresponding TCAM hardware search engine, the SL decoder is used to decode the search word and send it to the TL-TCAM hardware search engine array, and the decoding is to convert a search word SL corresponding to data in a TCAM hardware search engine table into a search word LSL corresponding to TL-TCAM hardware search engine table data, the effect is that TCAM adds a decoder, cooperates with the decoder and by lookup table method converts the TCAM table data to a new circuit unit that can be adapted to the added search line.

Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

Abstract: Certain aspects of the present disclosure generally relate to a circuit board with ground vias offset from associated ground bumps. One example circuit board generally includes a first signal connection terminal configured to connect a signal line of the circuit board to an integrated circuit (IC); a ground plane having a first ground connection terminal disposed adjacent to the first signal connection terminal, the first ground connection terminal being configured to provide a ground connection between the ground plane and the IC; and a first ground via associated with and disposed adjacent to the first ground connection terminal and coupled to the ground plane, wherein, from an overhead view of the circuit board, the first ground via is located at a position that is offset from a first axis on which the first signal connection terminal and the first ground connection terminal are disposed.

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

Abstract: A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.

Abstract: A shouldering type photographing support is provided, comprising a main frame for coupling components, on which at least one connecting base for fixing a lens or camera is provided; a shouldering assembly connected to the main frame, wherein the shouldering assembly being provided on a side of one end of the main frame and not in the same axis as the connecting base, and the shouldering assembly being located in the left rear or right rear of the at least one connecting base; and a supporting assembly connected to the main frame, wherein the supporting assembly comprises a chest-supporting assembly, arm-supporting assembly, handheld assembly and supporting leg assembly, the shouldering assembly and the supporting assembly together provide supporting at multiple points for the main frame.

Abstract: The present invention provides a driving system comprising two actuators for moving a stage through two elastic connectors; and a general apparatus/device comprising such a driving system, such as a machine tool, an analytical instrument, an optical microscope, and an apparatus of charged-particle beam such as electron microscope and an electron beam lithographical apparatus. When used in an electron microscope, the stage can be used as a specimen stage or a plate having apertures for electron beam to pass through. The novel stage driving system exhibits numerous technical merits such as simpler structure, better manufacturability, improved cost-effectiveness, and higher reliability, among others.

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex compute operation.

Abstract: A disclosed example includes selecting, by a mobile computing device, a model description for a predictive analytics model in response to a user-level application request including input data from an application of the mobile computing device, the model description created with a predictive analytics model description language, the model description received from a predictive analytics provider; comparing, by the mobile computing device, first data associated with the user-level application request with second data indicative of digital rights permissions associated with the model description; and executing, by the mobile computing device, an executable associated with the model description without providing the processor circuitry access to the executable and without providing the input data to the predictive analytics provider.