Abstract: Aqueous hydrocortisone sodium phosphate and monothioglycerol formulations are disclosed.

Abstract: This disclosure provides a resource tapping method, a resource tapping apparatus and an electronic device, and relates to the field of computer technology, in particular to the technical field of artificial intelligence, such as deep learning and machine learning. A specific implementation is as follows: obtaining operation data in M resource dimensions of a target cabinet, the M resource dimensions including a power resource, where M is a positive integer; determining a target power over-allocation value of the target cabinet based on the operation data, the target power over-allocation value being used for indicating an allowable power increment on the basis of a power rating of the target cabinet; and determining, based on the target power over-allocation value, a first quantity of additional servers deployable in the target cabinet.

Abstract: A method operating a Graphics Processing Unit (GPU) memory can be provided by accessing specified training parameters used to train a Deep Neural Network (DNN) using a GPU with a local GPU memory, the specified training parameters including at least a specified batch size of samples configured to train the DNN. A sub-batch size of the samples can be defined that is less than or equal to the specified batch size of samples in response to determining that an available size of the local GPU memory is insufficient to store all data associated with training the DNN using one batch of the samples. Instructions configured to train the DNN using the sub-batch size can be defined so that an accuracy of the DNN trained using the sub-batch size is about equal to an accuracy of the DNN trained using the specified batch size of the samples.

Abstract: One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point operations that are configurable to include two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions. The floating-point operations may include a first operation at a first precision and a second operation at a second precision. The first operation may include a multiply having at least one 16-bit floating-point input and the second operation may include an accumulate having a 32-bit floating-point input.

Abstract: One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.

Abstract: A rapid and automatic virus imaging and analysis system includes (i) electron optical sub-systems (EOSs), each of which has a large field of view (FOV) and is capable of instant magnification switching for rapidly scanning a virus sample; (ii) sample management sub-systems (SMSs), each of which automatically loads virus samples into one of the EOSs for virus sample scanning and then unloads the virus samples from the EOS after the virus sample scanning is completed; (iii) virus detection and classification sub-systems (VDCSs), each of which automatically detects and classifies a virus based on images from the EOS virus sample scanning; and (iv) a cloud-based collaboration sub-system for analyzing the virus sample scanning images, storing images from the EOS virus sample scanning, and storing and analyzing machine data associated with the EOSs, the SMSs, and the VDCSs.

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Abstract: An apparatus to facilitate neural network (NN) training is disclosed. The apparatus includes training logic to receive one or more network constraints and train the NN by automatically determining a best network layout and parameters based on the network constraints.

Abstract: Methods and apparatus relating to autonomous vehicle neural network optimization techniques are described. In an embodiment, the difference between a first training dataset to be used for a neural network and a second training dataset to be used for the neural network is detected. The second training dataset is authenticated in response to the detection of the difference. The neural network is used to assist in an autonomous vehicle/driving. Other embodiments are also disclosed and claimed.

Abstract: The present invention provides an apparatus of charged-particle beam e.g. an electron microscope comprising an in-column plasma generator for selectively cleaning BSE detector and BF/DF detector. The plasma generator is located between a lower pole piece of objective lens and the BF/DF detectors, but outside trajectory area of the charged-particles from the sample stage to the BF/DF detector.

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

Abstract: A metal sheet having a low friction coefficient and a low waviness. Multiple round or roughly-round small pits are distributed on the surface of the metal sheet. The diameter of a single pit ranges from 30 ?m to 150 ?m, and the overlap between adjacent pits is lower than 10%. On the surface of the metal sheet where the pits are located, the proportion of the area of pits per square millimeter of surface area is greater than 30%, and the difference between the quantities of pits in any unit square millimeter is less than 20%. By means of the proper design of surface microstructure, the friction coefficient and the waviness can be effectively reduced, thereby improving the forming and painting performance of the material.

Abstract: A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

Abstract: The application discloses a tension system optimization method for suppressing vibration of a cold tandem rolling mill. The method aims to suppress vibration occurring in a high-speed rolling process of a cold tandem rolling mill, and provides a rolling machine vibration determination index coefficient for effectively determining whether vibration occurs in a rolling machine.

Abstract: One embodiment provides a graphics processor comprising an instruction cache to store an instruction and a compute block configured to perform multiply-accumulate operations in response to execution of the instruction. The compute block includes a scheduler to schedule a plurality of threads for execution of the instruction and multiply-accumulate circuitry configured to execute the instruction via the plurality of threads, wherein the multiply-accumulate circuitry includes a plurality of functional units configured to process, in parallel via the plurality of threads, a corresponding plurality of matrix elements to multiply a first matrix and a second matrix, and to multiply the first matrix and the second matrix includes to multiply data elements in a row of the first matrix by corresponding data elements in a column of the second matrix to generate a plurality of products.

Abstract: One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread architecture, the general-purpose graphics compute unit to concurrently execute the first instruction and the second instruction.

Abstract: The present disclosure discloses a silicon nanowire chip and silicon nanowire chip-based mass spectrometry detection method. The detection method includes the following steps: step 1 of manufacturing a silicon nanowire chip, comprising: subjecting a monocrystalline silicon wafer to a surface washing pretreatment, a metal-assisted etching and a post-alkali etching to obtain a silicon nanowire chip with a tip, and performing a surface chemical modification or a nanomaterial modification on the silicon nanowire chip; step 2 of evaluating mass spectrometry performance of the silicon nanowire chip; and step 3 of performing a tip-contact sampling and in-situ ionization mass spectrometry detection.

Abstract: One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.

Abstract: A mechanism is described for facilitating smart collection of data and smart management of autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and combining a first computation directed to be performed locally at a local computing device with a second computation directed to be performed remotely at a remote computing device in communication with the local computing device over the one or more networks, where the first computation consumes low power, wherein the second computation consumes high power.