Patents by Inventor Xiaoming Chen

Xiaoming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Graphics processing integrated circuit package
    Patent number: 10540318
    Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.
    Type: Grant
    Filed: April 9, 2017
    Date of Patent: January 21, 2020
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Farshad Akhbari, Feng Chen, Dukhwan Kim, Narayan Srinivasa, Nadathur Rajagopalan Satish, Liwei Ma, Jeremy Bottleson, Eriko Nurvitadhi, Joydeep Ray, Ping T. Tang, Michael Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu
  • COMPUTE OPTIMIZATION MECHANISM
    Publication number: 20200020070
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 8-bit and/or 32 bit signed or unsigned integer elements.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • SMART AUTONOMOUS MACHINES UTILIZING CLOUD, ERROR CORRECTIONS, AND PREDICTIONS
    Publication number: 20200019844
    Abstract: A mechanism is described for facilitating smart collection of data and smart management of autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and combining a first computation directed to be performed locally at a local computing device with a second computation directed to be performed remotely at a remote computing device in communication with the local computing device over the one or more networks, where the first computation consumes low power, wherein the second computation consumes high power.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 16, 2020
    Applicant: Intel Corporation
    Inventors: Brian T. Lewis, Feng Chen, Jeffrey R. Jackson, Justin E. Gottschlich, Rajkishore Barik, Xiaoming Chen, Prasoonkumar Surti, Mike B. Macpherson, Murali Sundaresan
  • METHOD AND APPARATUS FOR GENERATING 3D AUDIO CONTENT FROM TWO-CHANNEL STEREO CONTENT
    Publication number: 20200008001
    Abstract: For generating 3D audio content from a two-channel stereo signal, the stereo signal (x(t)) is partitioned into overlapping sample blocks and is transformed into time-frequency domain. From the stereo signal directional and ambient signal components are separated, wherein the estimated directions of the directional components are changed by a predetermined factor, wherein, if changes are within a predetermined interval, they are combined in order to form a directional centre channel object signal. For the other directions an encoding to Higher Order Ambisonics HOA is performed. Additional ambient signal channels are generated by de-correlation and rating by gain factors, followed by encoding to HOA. The directional HOA signals and the ambient HOA signals are combined, and the combined HOA signal and the centre channel object signals are transformed to time domain.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 2, 2020
    Applicant: DOLBY LABORATORIES LICENSING CORPORATION
    Inventors: Johannes BOEHM, Xiaoming CHEN
  • INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING
    Publication number: 20190369988
    Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 5, 2019
    Applicant: Intel Corporation
    Inventors: HIMANSHU KAUL, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Method, system and equipment for automatically detecting and tracking blade
    Publication number: 20190370999
    Abstract: The present invention provides a method, a system and an equipment for automatically detecting and tracking a blade, used for tracking the blade of the wind power generator through an unmanned aerial vehicle. The unmanned aerial vehicle is provided with a cradle head, the cradle head controls a shooting angle of a camera, including the following steps: acquiring a blade video file through a camera, detecting at least one frame of the blade image in the blade video file, and extracting side edges of the blade region in the at least one frame of blade images; tracking and detecting the side edges of the blade region in temporally adjacent multi-frame blade images in the blade video file according to the side edges of the blade region; determining a center point of the blade region in each frame of the blade image; and adjusting the cradle head.
    Type: Application
    Filed: August 27, 2018
    Publication date: December 5, 2019
    Applicant: Shanghai Clobotics Technology Co., Ltd.
    Inventors: Xun LIU, Limin SHANG, Xiaoming CHEN, Hua YE, Yan KE
  • Compute optimization mechanism
    Patent number: 10489877
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • Instructions and logic to perform floating-point and integer operations for machine learning
    Patent number: 10474458
    Abstract: One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • ROLL FOR ROLLING SURFACE TOPOGRAPHY OF STEEL PLATE AND METHOD FOR MANUFACTURING SAME
    Publication number: 20190337032
    Abstract: A roll for rolling surface topography of a steel plate is disclosed. A plurality of raised textured points are arranged on a roll surface. The shape formed by a joint between each single textured point and the roll surface is circular or approximately circular. The circular shape has a diameter of 50˜150 ?m. Each single textured point has a raised height of 2˜12 ?m, and the overlap among adjacent textured points is lower than 10%. The quantity variance of the textured points per square millimeter of the roll surface is lower than 20%, and the coverage area ratio of the textured points in each square millimeter is 30˜90%. The method comprises performing surface treatment on a feed roll to control the surface roughness Ra of the roll to be smaller than 0.5 ?m; and performing layer-by-layer ablation on a surface material of the roll to form the textured points.
    Type: Application
    Filed: April 18, 2018
    Publication date: November 7, 2019
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Xiaoming CHEN, Shanqing LI, Kaifu YANG, Jizhe QUAN
  • COMPUTE OPTIMIZATIONS FOR NEURAL NETWORKS
    Publication number: 20190332903
    Abstract: One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a bipolar binary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the bipolar binary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Applicant: Intel Corporation
    Inventors: Kevin Nealis, Anbang Yao, Xiaoming Chen, Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha
  • PERSON TRACKING AND PRIVACY AND ACCELERATION OF DATA USING AUTONOMOUS MACHINES
    Publication number: 20190332869
    Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 31, 2019
    Applicant: Intel Corporation
    Inventors: MAYURESH M. VARERKAR, BARNAN DAS, NARAYAN BISWAL, STANLEY J. BARAN, GOKCEN CILINGIR, NILESH V. SHAH, ARCHIE SHARMA, SHERINE ABDELHAK, SACHIN GODSE, FARSHAD AKHBARI, NARAYAN SRINIVASA, ALTUG KOKER, NADATHUR RAJAGOPALAN SATISH, DUKHWAN KIM, FENG CHEN, ABHISHEK R. APPU, JOYDEEP RAY, PING T. TANG, MICHAEL S. STRICKLAND, XIAOMING CHEN, ANBANG YAO, TATIANA SHPEISMAN, VASANTH RANGANATHAN, SANJEEV JAHAGIRDAR
  • THIN FILM TRANSISTOR ARRAY SUBSTRATE, LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR
    Publication number: 20190319134
    Abstract: The present disclosure provides a low temperature poly-silicon thin film transistor. The low temperature poly-silicon thin film transistor includes a substrate, a poly-silicon layer formed at a surface of the substrate, an insulating layer, a gate electrode, a first control electrode, a second control electrode, a source electrode, and a drain electrode. The insulating layer covers the poly-silicon layer. A gap between the first control electrode and the gate electrode and a gap between the second control electrode and the gate electrode correspond to offset regions of the poly-silicon layer. Two heavily doped regions formed at the poly-silicon layer are respectively located besides the first control electrode and the second control electrode away from the offset regions. The source electrode and the drain electrode are respectively formed at the heavily doped regions.
    Type: Application
    Filed: December 24, 2016
    Publication date: October 17, 2019
    Inventor: Xiaoming CHEN
  • Method and apparatus for generating 3D audio content from two-channel stereo content
    Patent number: 10448188
    Abstract: For generating 3D audio content from a two-channel stereo signal, the stereo signal (x(t)) is partitioned into overlapping sample blocks and is transformed into time-frequency domain. From the stereo signal directional and ambient signal components are separated, wherein the estimated directions of the directional components are changed by a predetermined factor, wherein, if changes are within a predetermined interval, they are combined in order to form a directional center channel object signal. For the other directions an encoding to Higher Order Ambisonics (HOA) is performed. Additional ambient signal channels are generated by de-correlation and rating by gain factors, followed by encoding to HOA. The directional HOA signals and the ambient HOA signals are combined, and the combined HOA signal and the center channel object signals are transformed to time domain.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 15, 2019
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Johannes Boehm, Xiaoming Chen
  • COMPUTE OPTIMIZATIONS FOR LOW PRECISION MACHINE LEARNING OPERATIONS
    Publication number: 20190304053
    Abstract: Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland
  • COMPUTE OPTIMIZATION MECHANISM
    Publication number: 20190304054
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 16-bit and/or 32 bit floating-point elements.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • LOOKUP-TABLE HARDWARE SEARCH ENGINE
    Publication number: 20190278604
    Abstract: Lookup-table hardware search engine belongs to the field of information technology, and is used to improve the traditional TCAM hardware search engine to make the circuit performance higher. The technical points are: including SL decoder, TL-TCAM array, the data stored in the TL-TCAM hardware search engine is obtained by performing lookup table operation in the corresponding TCAM hardware search engine, the decoder is used to decode the search word and send it to the TL-TCAM hardware search engine array, the decoding is to convert a search word SL corresponding to data in a TCAM hardware search engine table into a search word LSL corresponding to TL-TCAM hardware search engine table data, the effect is that TCAM adds a decoder, cooperates with the decoder and by lookup table method converts the TCAM table data to a new circuit unit that can be adapted to the added search line.
    Type: Application
    Filed: December 22, 2017
    Publication date: September 12, 2019
    Inventors: Jianwei ZHANG, Guoqiang WU, Xiaoming CHEN, Yan YU
  • GNSS regional correction data decoding
    Patent number: 10408941
    Abstract: A correction message for regional GNSS data includes at least one network message and at least one cluster message. The at least one network message relates to stations of a network of stations within a region. The at least one cluster message relates to a subset of stations within the region. Network elements are extracted from the network message and cluster elements are extracted from the cluster message. Network elements and cluster elements are used to determine a position of a rover within the region.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: September 10, 2019
    Assignee: Trimble Inc.
    Inventors: Xiaoming Chen, Ulrich Vollath, Kendall Ferguson
  • Autonomous machines through cloud, error corrections, and predictions
    Patent number: 10410115
    Abstract: A mechanism is described for facilitating smart collection of data and smart management of autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and combining a first computation directed to be performed locally at a local computing device with a second computation directed to be performed remotely at a remote computing device in communication with the local computing device over the one or more networks, where the first computation consumes low power, wherein the second computation consumes high power.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: September 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Brian T. Lewis, Feng Chen, Jeffrey R. Jackson, Justin E. Gottschlich, Rajkishore Barik, Xiaoming Chen, Prasoonkumar Surti, Mike B. Macpherson, Murali Sundaresan
  • Compute optimizations for neural networks
    Patent number: 10410098
    Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including an input value and a quantized weight value associated with a neural network and an arithmetic logic unit including a barrel shifter, an adder, and an accumulator register, wherein to execute the decoded instruction, the barrel shifter is to shift the input value by the quantized weight value to generate a shifted input value and the adder is to add the shifted input value to a value stored in the accumulator register and update the value stored in the accumulator register.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Nealis, Anbang Yao, Xiaoming Chen, Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha
  • Instructions having support for floating point and integer data types in the same register
    Patent number: 10409614
    Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising instruction decode logic to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands having differing precisions and a general-purpose graphics compute unit including a first logic unit and a second logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform a first instruction operation on a first set of operands of the multiple operands at a first precision and a simultaneously perform second instruction operation on a second set of operands of the multiple operands at a second precision.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Barath Lakshmanan, Tatiana Shpeisman, Joydeep Ray, Ping T. Tang, Michael Strickland, Xiaoming Chen, Anbang Yao, Ben J. Ashbaugh, Linda L. Hurd, Liwei Ma