Patents by Inventor Xiaoming Chen

Xiaoming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190162214
    Abstract: A positioning locking mechanism of a rotational member comprising a rotational positioning member provided with a positioning groove; a rotational member pivotally connected with the rotational positioning member and rotating around the rotational positioning member; a positioning member arranged in the rotational member and movably meshed with the positioning groove; and a locking operation member arranged in the rotational member to control the motion of the positioning member. The positioning locking mechanism can effectively ensure that the positioning and locking of the rotational member cannot be invalid due to accident collision or component fatigue.
    Type: Application
    Filed: September 27, 2018
    Publication date: May 30, 2019
    Inventor: Xiaoming Chen
  • Publication number: 20190162228
    Abstract: A positioning locking mechanism of a rotational member having a rotational positioning member provided with a positioning groove; a rotational member pivotally connected with the rotational positioning member and rotating around the rotational positioning member; a positioning member arranged in the rotational member and movably meshed with the positioning groove; and a locking operation member arranged in the rotational member to control the motion of the positioning member. The positioning locking mechanism can effectively ensure that the positioning and locking of the rotational member cannot be invalid due to accident collision or component fatigue.
    Type: Application
    Filed: May 8, 2018
    Publication date: May 30, 2019
    Inventor: Xiaoming Chen
  • Publication number: 20190162362
    Abstract: A quick locking device having a fixing mount; a fixed pressing groove and a movable pressing groove arranged opposite thereto on the fixing mount; a pulling rod connected to the fixed pressing groove and the movable pressing groove, so as to adjust the opening and closing of the movable pressing groove; a pivot shaft; a cam lever pivotally connected to the pulling rod through the pivot shaft, so as to adjust the opening or closing distance between the fixed pressing groove and the movable pressing groove; and a rotational positioning locking mechanism installed in the cam lever, wherein the rotational positioning locking mechanism comprises a positioning groove formed on the pivot shaft, a positioning member arranged in the cam lever and movably engaged with the positioning groove, and a locking operation member controlling the movement of the positioning member.
    Type: Application
    Filed: April 19, 2018
    Publication date: May 30, 2019
    Inventor: Xiaoming Chen
  • Patent number: 10303953
    Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mayuresh M. Varerkar, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Sherine Abdelhak, Sachin Godse, Farshad Akhbari, Narayan Srinivasa, Altug Koker, Nadathur Rajagopalan Satish, Dukhwan Kim, Feng Chen, Abhishek R. Appu, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Publication number: 20190146800
    Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The streaming multiprocessor comprises multiple processing blocks including multiple processing cores. The processing cores include independent integer and floating-point data paths that are configurable to concurrently execute multiple independent instructions. A memory is coupled with the multiple processing blocks.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventors: ELMOUSTAPHA OULD-AHMED-VALL, BARATH LAKSHMANAN, TATIANA SHPEISMAN, Joydeep Ray, Ping T. Tang, Michael Strickland, Xiaoming Chen, Anbang Yao, Ben J. Ashbaugh, Linda L. Hurd, Liwei Ma
  • Publication number: 20190139182
    Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 9, 2019
    Applicant: Intel Corporation
    Inventors: Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha, Nadathur Rajagopalan Satish, Jeremy Bottleson, Farshad Akhbari, Altug Koker, Narayan Srinivasa, Dukhwan Kim, Sara S. Baghsorkhi, Justin E. Gottschlich, Feng Chen, Elmoustapha Ould-Ahmed-Vall, Kevin Nealis, Xiaoming Chen, Anbang Yao
  • Patent number: 10281587
    Abstract: The invention relates to generating correction information to be used to correct observations coming from a navigation satellite system (NSS) receiver in a region of interest. For each of a plurality of reference stations in said region, raw observations obtained by the reference station observing NSS multiple-frequency signals from a plurality of satellites over multiple epochs are received. Then, precise satellite information on the orbit position, clock offset, and biases of each satellite is obtained. For each reference station, ambiguities in the carrier phase of the received raw observations are estimated, using the precise satellite information and the position coordinates of the reference station. Geometric-free phase linear combination values are then computed based on the received raw observations together with the estimated ambiguities. The correction information is generated based on the computed geometric-free phase linear combination values.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: May 7, 2019
    Assignee: Trimble Inc.
    Inventors: Ralf Drescher, Xiaoming Chen
  • Publication number: 20190112242
    Abstract: The present application belongs to the field of energetic compounds, and particularly relates to the use of a perovskite-type compound ABX3 as an energetic material. As a finding of the present application, the structural characteristics of the perovskite type enables the type of compound to be highly stable, thus overcoming the unsafety of an explosive having poor stability in the prior art. Meanwhile, the structural characteristics of the compound, such as rich energetic ligands, as well as the alternately arranged oxidizing energetic anions and reducing organic cations in the space, endow the compound with excellent performance on instantaneously releasing energy at detonation. The resulting three-dimensional structure allows the compound to not only have an energetic material effect but also overcome shortcomings of some existing energetic materials.
    Type: Application
    Filed: August 11, 2017
    Publication date: April 18, 2019
    Applicant: YICHANG ENERGY MATERIALS TECHNOLOGY CORPORATION LIMITED
    Inventors: Weixiong ZHANG, Shaoli CHEN, Xiaoming CHEN
  • Patent number: 10255656
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • Publication number: 20190102515
    Abstract: Data segments derived from stored oligonucleotides or oligos are decoded, each oligo comprising nucleotides representing information units distributed within segment addresses and payloads, the addresses enabling to order the payloads. The addresses are extracted and the payloads are ordered in function of those addresses. The segments are further clustered into segment clusters in function of edit distances between reference addresses and the extracted addresses, each of those clusters being associated with one of the reference addresses. Cluster payloads associated respectively with at least part of the clusters are determined, and those cluster payloads are ordered in function of the reference addresses of the clusters associated with the cluster payloads.
    Type: Application
    Filed: March 6, 2017
    Publication date: April 4, 2019
    Inventors: Xiaoming Chen, Meinolf Blawat, Klaus Gaedke, Ingo Huetter
  • Patent number: 10242423
    Abstract: One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction; the at least one single instruction to cause at least a portion of the GPU to perform a floating-point operation on input having differing precisions; and the floating-point operation is a two-dimensional matrix multiply and accumulate operation.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland
  • Publication number: 20190073582
    Abstract: An apparatus and method for local quantization for convolutional neural networks. For example, one embodiment of an apparatus comprises: a convolutional neural network module comprising a neuron network structure to perform pattern recognition within an input image using a set of input image values; and a quantization module to quantize input image values to reduce processing requirements within one or more stages of the neuron network structure; the quantization module to perform quantization of each of a plurality of patches of the input image using a first quantization policy to generate a first matrix of quantized input data and to perform quantization of each of a plurality of kernel data using a second quantization policy to generate a second matrix of quantized kernel data.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 7, 2019
    Inventors: Yi YANG, Chen FENG, Dai YAN, Xiaoming CHEN
  • Publication number: 20190069115
    Abstract: Currently there is no simple and satisfying way to create 3D audio from existing 2D content. The conversion from 2D to 3D sound should spatially redistribute the sound from existing channels. From a multi-channel 2D audio input signal (x(k)(t)) a 3D sound representation is generated which includes an HOA representation Formula (I) and channel object signals Formula (II) scaled from channels of the 2D audio input signal. Additional signals Formula (III) placed in the 3D space are generated by scaling (21, 222; 41, 422; Formula (IV)) channels from the 2D audio input signal and by decorrelating (24, 25; 44, 45, 451; Formula (V)) a scaled version of a mix of channels from the 2D audio input signal, whereby spatial positions for the additional signals are predetermined. The additional signals Formula (III) are converted (27; 47) to a HOA representation Formula (I).
    Type: Application
    Filed: November 11, 2016
    Publication date: February 28, 2019
    Applicant: DOLBY INTERNATIONAL AB
    Inventors: Alexander KRUEGER, Johannes BOEHM, Sven KORDON, Xiaoming CHEN, Stefan ABELING, Florian KEILER, Holger KROPP
  • Publication number: 20190047624
    Abstract: A side rail for a motor vehicle sub-frame includes (a) a first component having a first extrusion axis and (b) a second component having a second extrusion axis wherein the first and second components are joined with the first extrusion axis and the second extrusion axis forming an included angle of between 60 and 90 degrees.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 14, 2019
    Inventors: Xiaoming Chen, David Anthony Wagner, Gerald J. Heath, Michael Musa Azzouz, Tsung-Hsiun Li
  • Publication number: 20190047623
    Abstract: A cross member for a motor vehicle sub-frame includes (a) a hollow body having an extrusion axis and (b) a wall having a first edge and a second edge. The wall is positioned inside and extends across the hollow body with the first edge and the second edge joined to the hollow body.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 14, 2019
    Inventors: Xiaoming Chen, David Anthony Wagner, Gerald J. Heath, Michael Musa Azzouz, Tsung-Hsiun Li
  • Patent number: 10186011
    Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha, Nadathur Rajagopalan Satish, Jeremy Bottleson, Farshad Akhbari, Altug Koker, Narayan Srinivasa, Dukhwan Kim, Sara S. Baghsorkhi, Justin E. Gottschlich, Feng Chen, Elmoustapha Ould-Ahmed-Vall, Kevin Nealis, Xiaoming Chen, Anbang Yao
  • Patent number: 10160491
    Abstract: A sub-frame assembly supports a pair of wheels on a vehicle. The base may be an extrusion having a matrix of panels extending in a vertical direction. The sub-frame assembly has control arm brackets disposed on opposing ends of the base and attachment towers extending above the brackets providing attachment points to connect portions of an independent suspension to the vehicle and support a pair of wheels. The base, control brackets and attachment towers may be individual modular pieces. Left and right hand control brackets and attachment towers may be provided by respective unitary support pieces attached to opposing ends of the base. The unitary support pieces may be extrusions having panels extending in a transverse direction, nonaxial to the base. The base, control arm brackets and attachment towers, alternatively, may be provided by a single unitary extrusion having a matrix of panels extending in a transverse direction.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 25, 2018
    Assignee: Ford Global Technologies, LLC
    Inventors: John Joseph Uicker, Sanjay Mehta, Patrick Marchena, Xiaoming Chen, David Anthony Wagner, Michael M. Azzouz, Allen Li, Gerald Heath, Sunil K. Kasaragod
  • Publication number: 20180315398
    Abstract: One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.
    Type: Application
    Filed: October 18, 2017
    Publication date: November 1, 2018
    Applicant: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Publication number: 20180315399
    Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.
    Type: Application
    Filed: November 21, 2017
    Publication date: November 1, 2018
    Applicant: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Publication number: 20180315159
    Abstract: One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction; the at least one single instruction to cause at least a portion of the GPU to perform a floating-point operation on input having differing precisions; and the floating-point operation is a two-dimensional matrix multiply and accumulate operation.
    Type: Application
    Filed: October 20, 2017
    Publication date: November 1, 2018
    Applicant: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland