Patents by Inventor Xiaowei Deng
Xiaowei Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240110537Abstract: The present application relates to the field of fuel filter components of internal combustion engines, and discloses a fuel filter element, including a support tube, a filter medium, and an upper cover plate and a lower cover plate. The upper cover plate is provided with a first channel. The lower cover plate is provided with a second channel. An air duct is arranged between the upper cover plate and the lower cover plate. The air duct communicates with the first channel and the second channel, and the air duct is positioned on an outer side of the filter medium. The filter medium is arranged between the air duct and a fuel feeding position, such that the stability of a fuel supply pressure and an exhaust state of this fuel filter element is enhanced.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: ZHEJIANG WEITAI AUTOMOBILE PARTS CO., LTD.Inventors: Jianbin Cheng, Yu Zhang, Shixian Lan, Qinglin Deng, Xiaowei Ying
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Publication number: 20240109009Abstract: The present application relates to the field of fuel filter components of internal combustion engines, and discloses a filter with a rotating device, including a filter element and the rotating device installed on the filter element. The filter element is provided with a clamping structure matched with the rotating device. The rotating device is provided with an eccentrically arranged fuel return plug, an internal opening, and a drive portion structure. By arranging the rotating device, the service life of this filter is prolonged. By forming the internal opening and arranging the fuel return plug, the installation efficiency and convenience of this filter are improved.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: ZHEJIANG WEITAI AUTOMOBILE PARTS CO., LTD.Inventors: Jianbin Cheng, Yu Zhang, Qinglin Deng, Xiaowei Ying
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Publication number: 20240084767Abstract: The present application discloses a fuel-water separation filter element capable of exhausting gas, and a filter. The filter element includes a filter element frame, a filter medium, and an exhaust valve assembly. An upper end cover and a lower end cover are arranged at an upper end and a lower end of the filter element frame. The upper end cover is provided with a recess surface along an axial direction of the filter element frame. The exhaust valve assembly includes a valve seat and a valve element. The valve seat and the recess surface form an exhaust cavity communicating with the inside of the filter element. The exhaust valve assembly in the present application can effectively exhaust gas in the filter.Type: ApplicationFiled: October 10, 2022Publication date: March 14, 2024Applicant: ZHEJIANG WEITAI AUTOMOBILE PARTS CO., LTD.Inventors: Jianbin Cheng, Yu Zhang, Qinglin Deng, Xiaowei Ying
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Publication number: 20240082762Abstract: The present application provides a fuel-water separation filter element and a fuel filter. The filter element includes a fuel duct, a water blocking tube, and a filter medium. An upper cover plate is connected to one end of the fuel duct. The upper cover plate is formed with an air collection cavity in the fuel duct. The water blocking tube is provided with a water blocking portion positioned in the fuel duct, and a vent pin axially extends from an end surface of one end of the water blocking portion. The vent pin respectively communicates with the air collection cavity and the outside. During operation of the filter element in the present application, gas mixed into a fuel supply system may be effectively exhausted.Type: ApplicationFiled: October 10, 2022Publication date: March 14, 2024Applicant: ZHEJIANG LAIEN FILTRATION SYSTEM CO., LTD.Inventors: Yu Zhang, Jianbin Cheng, Xiaowei Ying, Qinglin Deng
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Publication number: 20240082758Abstract: The present application discloses an electrostatically conductive filter element. An annular end cover made of a conductive material is connected to one end of a filter medium of the filter element. An annular raised wall axially extends from an inner opening of the annular end cover. Conductive portions radially extending inwards and configured to be in hard connection with an external conductive device are arranged on an inner surface of the annular raised wall. During use of this filter element, the conductive portions can be stably electrically connected to the external conductive device, and the static electricity generated by the filter medium is dissipated to the outside by the external conductive device.Type: ApplicationFiled: October 10, 2022Publication date: March 14, 2024Applicant: ZHEJIANG LAIEN FILTRATION SYSTEM CO., LTD.Inventors: Yu Zhang, Xiaowei Ying, Jianbin Cheng, Qinglin Deng
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Patent number: 11495301Abstract: In one example a semiconductor device has a data latch that includes first and second transmission gates and first and second inverters. The first inverter is connected between a first terminal of the first transmission gate and a first terminal of the second transmission gate. The second inverter is connected between a second terminal of the first transmission gate and a second terminal of the second transmission gate. The data latch is configured to store a datum received at the connection between the first transmission gate and the second inverter, and to store a datum received at the connection between the second transmission gate and the first inverter.Type: GrantFiled: March 31, 2021Date of Patent: November 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaowei Deng, Yunchen Qiu, David Joseph Toops
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Patent number: 11355182Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.Type: GrantFiled: October 31, 2017Date of Patent: June 7, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaowei Deng, Wah Kit Loh
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Publication number: 20210304824Abstract: In one example a semiconductor device has a data latch that includes first and second transmission gates and first and second inverters. The first inverter is connected between a first terminal of the first transmission gate and a first terminal of the second transmission gate. The second inverter is connected between a second terminal of the first transmission gate and a second terminal of the second transmission gate. The data latch is configured to store a datum received at the connection between the first transmission gate and the second inverter, and to store a datum received at the connection between the second transmission gate and the first inverter.Type: ApplicationFiled: March 31, 2021Publication date: September 30, 2021Inventors: Xiaowei Deng, Yunchen Qiu, David Joseph Toops
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Publication number: 20180068713Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.Type: ApplicationFiled: October 31, 2017Publication date: March 8, 2018Inventors: Xiaowei Deng, Wah Kit Loh
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Patent number: 9805788Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.Type: GrantFiled: July 31, 2015Date of Patent: October 31, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaowei Deng, Wah Kit Loh
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Patent number: 9576643Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.Type: GrantFiled: July 31, 2015Date of Patent: February 21, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaowei Deng, Wah Kit Loh
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Patent number: 9472268Abstract: An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a plurality of transistors (200,202). A first memory cell (FIG. 2) is arranged to store a data signal in response to an active write word line (WWL) and to produce the data signal in response to an active read word line (RWL). A test circuit (104) formed on the integrated circuit is operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell (FIGS. 7-10).Type: GrantFiled: June 27, 2011Date of Patent: October 18, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaowei Deng, Wah Kit Loh
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Patent number: 9466356Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.Type: GrantFiled: July 31, 2015Date of Patent: October 11, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaowei Deng, Wah Kit Loh
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Patent number: 9455021Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.Type: GrantFiled: April 5, 2012Date of Patent: September 27, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaowei Deng, Wah Kit Loh
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Patent number: 9412437Abstract: An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a plurality of transistors (200, 202). A first memory cell (FIG. 2) is arranged to store a data signal in response to an active write word line (WWL) and to produce the data signal in response to an active read word line (RWL). A test circuit (104) formed on the integrated circuit is operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell (FIGS. 7-10).Type: GrantFiled: January 9, 2014Date of Patent: August 9, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaowei Deng, Wah Kit Loh
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Patent number: 9208899Abstract: An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included.Type: GrantFiled: May 5, 2010Date of Patent: December 8, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaowei Deng, Wah K. Loh
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Patent number: 9208902Abstract: An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.Type: GrantFiled: October 29, 2009Date of Patent: December 8, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Beena Pious, Xiaowei Deng, Wah Kit Loh, Jon Lescrenier
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Patent number: 9208832Abstract: A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.Type: GrantFiled: December 21, 2012Date of Patent: December 8, 2015Assignee: TEXAS INSTURMENTS INCORPORATEDInventors: Xiaowei Deng, Yang Yi, Wah Kit Loh
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Publication number: 20150348615Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.Type: ApplicationFiled: July 31, 2015Publication date: December 3, 2015Inventors: Xiaowei Deng, Wah Kit Loh
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Publication number: 20150340081Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.Type: ApplicationFiled: July 31, 2015Publication date: November 26, 2015Inventors: Xiaowei Deng, Wah Kit Loh